hi,
I'm having trouble initializing some memory in a verilog include file. If I do the following :
BRAM16_S9 memory ( ... ); // synthesis attribute init_00 of memory is "...."
Everything works fine.
However, I really want to have the memory initialization done in an include file (because it is generated), like such:
BRAM16_S9 memory ( ... ); `include "init.v"
(with the init.v file containing the // synthesis attribute ...).
But then I get an error from XST:
Cannot find in module
Is there a way to make this work ?
Arlet