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EDK core wrapping and include files

Hi !

we are wrapping some of our IP Cores for EDK. That way they can be automatically instantiated in to a SoC and easily integrated.

However, we seem to have problems with include files. Our cores are written in Verilog, and we don't know how to specify the proper include path for include files. When EDK compiles the IP Core it can not find the include files unless we manually copy them to a local working directory.

Does anybody know how to solve this problem ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Your Partner for IP Cores, Design, Verification and Synthesis

Reply to
Rudolf Usselmann
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Good plan! I would love to see a wishbone -> opb bridge to get some of that great opencores.org stuff into microblaze projects.

Maybe the .pao (peripheral analyse order) file has something to do with it? It lives in pcores/mycore/data/... I've only used it for VHDL cores, but it probably has a role to play with verilog as well.

Hope this hepls,

John

Reply to
John Williams

opencores stuff is actually being used in OPB/Microblaze systems at many places :)

the .PAO only specifies the order of compilation, but:

xyz_defines.v

that contains no modules but only defines would not produce any compiled code and as such will be ignored :(

as much as I understand the all EDK core approuch is built on assumption that all parameters are propagated from top to bottom. So an include file with parameters clearly brakes the logic behind EDK cores.

the only working solution is to prevent the EDK to synthesise the core and rerun synthesis for this single core from shell script (where the approp path to include dir can be given), optionally a build script could be made that copies the include file automatically to working dir what is not a good solution of course

EDK support for verilog has been always a bit behind the VHDL support so maybe this problem gets and official fix too someday, or maybe some trick exist already :)

Antti

Reply to
Antti Lukats

There are some issues depending if the 'include is defined within the scope of the module or outside the scope.

Managing with PAO for `include outside module boundaries may work for synthesis since all the core's HDL are bundled together into a single project file when synthesizing. However, (behavioral) simulation compiles each source file separately, so it doesn't work in the sim flow as things currently stand.

As a current workaround, you can treat XST as a 3rd party synth tool executed outside platgen.

Change the MPD option "OPTION IMP_NETLIST=TRUE" to FALSE.

There is an app note about synplify integration into EDK. The flow is the same for XST outside of EDK. Make the appropriate subsitutions, and modify xst options where necessary to include -vlgincdir.

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This will allow you to run reiterati> However, we seem to have problems with include files. Our

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
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Reply to
Paulo Dutra

Where ?

Reply to
E.S.

in secret places, I did not say those designs are in public, only that wishbone peripherals are in use in OPB based systems.

Antti

Reply to
Antti Lukats

Hello,

It was suggested in a previous posting by Paulo Dutra to use XST as a

3rd party synthesizer in EDK to use the -vlgincdir XST option
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.

In the latest version of EDK 7.1i can we sidestep this work-around and set an option directly in EDK? I have been looking in the EST guide (Embedded System Tools Reference Manual) and the GUI as well, but I haven't found any pointers.

Thanks,

NN

Reply to
Nju Njoroge

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