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initializing array of registers in XST

Steve, Peter and Austin-

Can you give definitive instructions -- or point me to who can -- for initializing an array of registers?

I need to initialize an array of registers in one way, set values differently upon Reset, and set values differently again during normal operation. I have this code:

reg [31:0] array [11:0];

// synthesis attribute INIT of array is 64'h0C0001820C000080;

which is intended to initialize the first 2 elements of the array, but doesn't set any bits although XST appears to "accept" the INIT attribute. What is needed? The whole 384 bits set with one number? Can this be done using 384'hxxxx... syntax?

I have opened a webcase through our local FAE, but after about 3 weeks have no clear answers other than to instantiate a RAM using CoreGen and use a .coe file, or read in a .dat file for simulation purposes but not synthesis. To use a RAM I would have to switch the array row/column to get XST to recognize asynchronous reads, and I have done that in other cases, but in this case I can't because I actually need 32-bit registers (they are accessible via a host processor).

For something like array initialization, there has to be a solid answer

-- hopefully some actual code showing how to do it.

Thanks.

-Jeff

Reply to
Jeff Brower
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Jeff; I don't have an answer for you, but since your code appears to be in verilog, I wonder if you'd get a response by posting in comp.lang.verilog.

-Dave P

Reply to
Dave Pollum

ISE 8 supports initialization of registers in an initial block, so

initial begin array[0]=1234; array[1]=5678; . . array[11]=0101; end

should do the trick.

-- Brian

Jeff Brower wrote:

Reply to
Brian Dam Pedersen

Brian-

Thanks Brian for your reply.

For simulation only? Or will this work for synthesis.

-Jeff

Reply to
Jeff Brower

Dave-

Thanks very much for your reply. Yes posting on the Verilog group might bring some ideas so I will do that.

But at the base, this is an XST issue. I can use UCF file, synthesis attribute -- whatever works. I just need to know what works in XST, for Xilinx FPGA devices, and be done with it.

-Jeff

Reply to
Jeff Brower

IIRC, xilinx initial values (after config) and built-in set/reset values must be the same (in fact, I know synplicity will take the reset value for the initial value). If you really need "reset" values different from initial ones, then you'll have to code a synchronous reset in with your logic. You'd have to be careful that it does not confuse your "logic" reset with a built-in reset function. Maybe if you coded a reset for the initial value (then hardwired it to optimize it out), and subsequent to that, a secondary "reset" function, that might work:

This is in vhdl, but here's what I'd try:

init

Reply to
Andy

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