Hi,
I have this in my .syr report file from XST:
Set property "equivalent_register_removal = no" for signal . Set property "equivalent_register_removal = no" for signal . ... Register equivalent to has been removed
I really don't understand why bar and foo are being merged when the tool knows they are not supposed to be. Can anyone please tell me how I can stop registers from being merged?
I think this code used to work properly, and the problem may be due to a bug in XST 6.2.3.
BTW, the relevant Verilog source is:
// synthesis attribute equivalent_register_removal of foo is no; // synthesis attribute equivalent_register_removal of bar is no;
reg foo; reg bar;
always @(posedge clk) begin foo