Hello.
I know this has been asked a zillion times before, but I want to know if it is currently possible to initialize inferred Block RAM using Verilog in XST, like it is possible to do using VHDL. Else, are there plans to include this feature anytime soon?
Best regards.
-- /"However, what if it does matter, and we are PabloBleyerKocik / missing something fundamental that could pbleyer2004 / change the way we see the world?" @embedded.cl / -- One Little Wrong Assumption, Darren Ashby