Xilinx Timing Constraints

There doesn't appear to be any way to put timing constraints on the internal signals of a design. I have a fast clock and a slow clock and it would be best if I could put a timing constraint on the fast signals.

When the editor opens up I see GLOBALS, PORTS, ADVANCE and MISC. Where are the signals? And how does Xilinx track signals through the VHDL sysnthesis inferrence process anyway? Seems like a lot of my signals are gone or renamed when I poke around in the layout editor.

One thing I have found is that you can double click the boxes in the editor and up pops a nice description of what the constraint does. I found this by accident.

I also have GLOBALS that I didn't expect. I have an oscin, OK, my oscillator input, but I also have a devounced switch signal , which granted, goes to a lot of components, but still considered a nearly DC value. What do I put here, 1000ns?

You can put a constraint from anything to anything in the UCF file. You >can also put period constraints on all of your clocks. Read the CGD manual.

By the way. The CGD manual is a 900 plus page doc. Best if one zone into the strategy chapter first, I suppose, or else read 137 pages leading up to this chapter.

Where is the Getting Started tutorial on this subject?

b r a d @ a i v i s i o n . c o m

Reply to
Brad Smallridge
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Timing constraints are applied to paths, not signals. You may well have different timing constraints on different paths that end at the same node or start from the same node. So a timing constraint must be applied to a path (or paths) between a set of starting points and a set of ending points.

Clocks can be constrained to a period which will then be the default constraint on all paths ending on the FFs driven by that clock. But still you need to think *paths*.

Timing constraint design is the one area of FPGA design that is not well taught and is subject to errors with little means of verification. I am surprised that after being used for so many years, timing constraints have not caught up with the logical part of chip design in terms of verification. I can perform simulations on the logic and measure the coverage of my test vectors. But I have no way to verify that my timing constraints are correct and are doing what I want them to do.

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Rick "rickman" Collins

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Reply to
rickman

OK well how do you apply a restraint to a path then?

Reply to
Brad Smallridge

I indicated that in my other post. You specify sets of starting points (which can be FFs, SRLs, any other synchronous elements or IOB inputs) and a set of end points (FFs SRLs, any other synchronous elements or IOB outputs). Timing constraints are applied between the starting points and the ending points.

A signal connects two objects which can include LUTs and other logic elements. These objects are connected by signals. But specing the time for a given signal is typically not useful since that is only a part of a path between timing end points.

Does that make more sense? I was around when Xilinx first introduced this method of timing constraints. It seemed counter intuitive at first. But I learned that it was the only practical way to specify timing. So think in terms of paths between timing end points, not signals.

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Rick "rickman" Collins

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rickman

internal

You only need to constraint the fast clock. This constraint will be used to place/route all the signals that are clocked by the fast clock.

HTH, Jim snipped-for-privacy@yahoo.com (remove capital letters)

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Reply to
Jim Wu

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