There doesn't appear to be any way to put timing constraints on the internal signals of a design. I have a fast clock and a slow clock and it would be best if I could put a timing constraint on the fast signals.
When the editor opens up I see GLOBALS, PORTS, ADVANCE and MISC. Where are the signals? And how does Xilinx track signals through the VHDL sysnthesis inferrence process anyway? Seems like a lot of my signals are gone or renamed when I poke around in the layout editor.
One thing I have found is that you can double click the boxes in the editor and up pops a nice description of what the constraint does. I found this by accident.
I also have GLOBALS that I didn't expect. I have an oscin, OK, my oscillator input, but I also have a devounced switch signal , which granted, goes to a lot of components, but still considered a nearly DC value. What do I put here, 1000ns?
By the way. The CGD manual is a 900 plus page doc. Best if one zone into the strategy chapter first, I suppose, or else read 137 pages leading up to this chapter.
Where is the Getting Started tutorial on this subject?
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