There doesn't appear to be any way to put timing constraints on the internal signals of a design. I have a fast clock and a slow clock and it would be best if I could put a timing constraint on the fast signals.
Xilinx Constraints
Sep 28, 2004
3 Replies
You can put a constraint from anything to anything in the UCF file. You can also put period constraints on all of your clocks. Read the CGD manual.
Not quite. I had a similar problem with a high frequency clock input that is divided down inside the CPLD and the low freq clock distributed to all flipflops on a global clock net. Added a NET "" BUFG = CLK; constraint to the UCF but it's appily ignored and doesn't even appear in the constraints editor (the comments, however, do appear). I am using the ``free'' tools that come with the ISE 6.2i WebPack, BTW.
I did but that did not help too much as explained above.
Cheers, Chris
manual.
I'm not sure what you are saying. But if you put a clock period constraint on a net, it may not be used if the signal does not pass through a BUFG. Have you checked to see if a BUFG was used for this internally generated clock?
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required