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timing constraints... again

Hi all, no metter how hard I try, I couldn't find an appropriate way to set timing constraints to my project. The thing is, I create .xcf file, add it to the project, run synthesis, run translate, map and par and the effect is that all of my timing constraints are met. When I run the Timing Analysis, the reported clk period is even shorter than the one I need. Ok, I run simulation using ModelSim and .sdf and .vhd files which ISE PAR generated - and get simulation errors caused by too short clk period! How can I be sure that the tool 'understood' my constraints and implemented them as well? Thanks in advance! Marija

Reply to
Marija
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Hi Christian, I did change the reesolution to a ps, but the timing constraints is in ns, anyway. Still, it doesn't work :( Marija

Reply to
Marija

Hi Marija,

maybe you didn't change your simulation resolution to ps? (it is the -t option, or can also be found in a pull down menu in the ModelSim GUI)

Christian

Reply to
Christian Haase

Another possibility is that your constraints are not actually constraining the signals you think they are. For PERIOD constraints make sure that you place the constraint after the DCM (pin period constraints don't always propagate through DCM or DLL). A good thing to check is the place and route report, which has a clock report and a constraint report at the end. Make sure your PERIOD constraints cover all listed clocks. Look at the constraint report for "N/A" entries which may indicate constraints that cover no paths.

Reply to
Gabor Szakacs

there are two possibility one u may not have apply reset for long enough time ,which will not initialise internal logic properly(this will be case if u r using asyncronous reset) nother possibility is if ur toplevel entity has bidirectional port then dont forget to use pullup/pulldown resistor model in test bench let me know is this help u or not

Reply to
khamkar77

hi Marija there are two possibility one u may not have apply reset for long enough time ,which will not initialise internal logic properly(this will be case if u r using asyncronous reset) nother possibility is if ur toplevel entity has bidirectional port then dont forget to use pullup/pulldown resistor model in test bench let me know is this help u or not

Reply to
khamkar77

Kindly post in plain text in future.

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Jonathan Bromley, Consultant

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Jonathan Bromley

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