Hi all,
I am confused with the "Clock to Setup on destination clock " section of the report. I am using differential clocks and the data doesn't seem right. Here is an example:
Clock to Setup on destination clock clk_dco_N
---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ clk_dco_N | 5.280| | | | clk_dco_P | 5.294| | | |
---------------+---------+---------+---------+---------+
This seems to contradict to the achieved 4.7 ns clock period on the internal clk_dco if I only understand correctly what this spec means... According to the Xilinx Answer Database this means the Q of a flip-flop that is running on one of the "source" clocks will reach the D of a flip-flop that is running on the "destination" clock (in this case clk_dco_N) in no more than "X"ns. Does this make sense at all for differential clocks?
/Mikhail