Actel timing constraints

I need to write some timing constraints for an ProAsic device. The Designer tool doesn't seem to cater for what I need; as follows:

FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) captures data on the clk falling edge (Same clock with very low skew to both devices) Similarly Actel outputs data on clk falling edge & Xilinx capture on rising edge. I have the Xilinx input & output delays and the clock period is 30 ns. The clock M/S ratio is 40/60 though, so the total allowed time from one device clocking out to the other device clocking in is therefore

12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns.

So how do I apply the constraints to my Actel chip; I've never used an SDC file, so some tips or pointers to examples would be useful.

TIA, Niv

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Niv (KP)
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