Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?

I have a problem with a xilinx virtex2 design, and specifying the timing constraints for a pair of clocks in the design. Most of the design is clocked by either a x1 clk, or a div2 clk (which is hence half the frequency). Both the x1 and div2 clock are generated in a dcm, locked to a x1 input clock. I select which clock to use via a global clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX, which is x1 so that I can be sure the circuitry driven by this clock will run at the faster x1 clock rate. I also put timing constraints on the two clocks out of the dcm, and the input clock pin. The Post PAR timing analyser tells me that there are no timing errors. The design is fine most of the time, but occasionally I get problems where part of the design stops working correctly, but is fixed by a new par. I investigated the timing more carefully, and used the constraints interaction report from the timing analyzer to see what might be going on. What I find in that report is that my timing constraint on the BUFGMUX output clock is shown to be overridden by the div2 clock specification, which is half the frequency. This may explain why I'm having problems. Nearly 2 months ago I contacted european xilinx support, but the guy dealing with my case says he isn't an expert on timing, and keeps coming back (supposedly after discussion with a more expert engineer) with ideas to try, such as putting TIG on the clocks etc. None of these have worked. I'm not totally sure the guy understands my problem. Does anyone have experience with this type of problem, or have any ideas how I can escalate the problem with Xilinx, and speak to a more knowledgeable engineer ? Regards Tony Benham

--
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
 Click to see the full signature
Reply to
Tony Benham
Loading thread data ...

Tony,

File a case with the hotline via the support.xilinx.com web page.

Aust> I have a problem with a xilinx virtex2 design, and specifying the timing

Reply to
Austin Lesea

Consider using div2 as a clock enable and clocking everything with x1.

-- Mike Treseler

Reply to
Mike Treseler

Put your timing constraint on the clkin of the DCM, don't put any constraints on the outputs of the DCM. The Xilinx tools will figure calculate the right constraints for the outputs and apply the worst case constraint. If that doesn't work then add a FFS to FFS constraint.

Reply to
B. Joshua Rosen

Please let me emphasize Mike's suggestion. There has been a series of problem reports in this ng, relating to clock manipulations. There is this simple general cure: Use a single global clock, and do the rest with selective clock enable. You save yourself a lot of headache and wasted time and effort. This should always be your first and obvious solution. Clock gating and other clock manipulation tricks should be the "solution of last resort" when CE cannot be used for some special reason.

Th>

Reply to
Peter Alfke

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.