Timing constraints on ISERDES

Using the ISERDES primitive in Virtex 4 in DDR mode (for data input from an ADC), what timing constraints should be applied?

In particular, I want to know the maximum data update rate (or alternatively, maximum source-synchronous clock frequency) that can be used to get the data into the FPGA. I assume this is limited by pin capacitance or other physical constraints, but don't know what it is in my design.

For example, say I have a single data input DATA and a single source-synchronous clock CLK (both of which come from the ADC). They are both LVDS, so I used IBUFDS. Both enter separate ISERDES. I use the "direct" combinatorial output of the CLK ISERDES (O) to feed a BUFIO, the output of which becomes the CLK for both ISERDES. This also feeds a BUFR with /2 divider, which feeds CLKDIV on both. I then get 4 demultiplexed outputs of DATA Q0-3, which can then feed a FIFO or DSP core.

So far I have applied a clock frequency constraint to the O output of the CLK ISERDES, and that is all. But the timing analyser only seems to check the CLKDIV constraints for the data outputs in the cores that follow, not the ISERDES itself...

Any enlightenment would be much appreciated.


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