Xilinx ISE 4.2 Unisim Block RAM bug?

Hello,

I developed my own synchronous FIFO buffer using Virtex Block RAM. However, when I try to simulate it on ModelSim XE 5.5e and 5.7c with ISE WebPACK 4.2's Unisim library, I get the following error messages.

# ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:690 ns, posedge CLKB &&& clkb_enable:690 ns, 100 ps ); # Time: 690 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:690 ns, posedge CLKB &&& clkb_enable:690 ns, 100 ps ); # Time: 690 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:720 ns, posedge CLKB &&& clkb_enable:720 ns, 100 ps ); # Time: 720 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:720 ns, posedge CLKB &&& clkb_enable:720 ns, 100 ps ); # Time: 720 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:750 ns, posedge CLKB &&& clkb_enable:750 ns, 100 ps ); # Time: 750 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_31_16 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S16_S16.v(453): $recovery( posedge CLKA:750 ns, posedge CLKB &&& clkb_enable:750 ns, 100 ps ); # Time: 750 ns Iteration: 2 Instance: /FIFO_Testbench_Top/FIFO_Inst/BRAM_15_0 . . . . .

The above error messages were displayed when the FIFO contains one entry, and the user logic tried to do simultaneous read/write of the FIFO. But if the FIFO contains two or more entries, simultaneous read/write of the FIFO doesn't display the above error message, and the FIFO functions correctly. When the FIFO's RAM (Virtex Block RAM in dual-port mode.) is replaced with Verilog's generic RAM, the FIFO functions correctly, so at this point I suspect that something is wrong with Unisim's Virtex Block RAM. Next thing I tried was to simulate synchronous version of a FIFO buffer (fifoctlr_cc.v) in Xilinx Application Note 175 with the same testbench code I used for testing my own FIFO. Interestingly, I got error messages very similar to what I got with my own FIFO.

# ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374): $recovery( posedge CLKB:690100 ps, posedge CLKA &&& clka_enable:690100 ps, 100 ps ); # Time: 660100 ps Iteration: 1 Instance: /fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374): $recovery( posedge CLKB:720100 ps, posedge CLKA &&& clka_enable:720100 ps, 100 ps ); # Time: 720100 ps Iteration: 1 Instance: /fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1 # ** Error: ../../../xilinx_webpack/verilog/src/unisims/RAMB4_S8_S8.v(374): $recovery( posedge CLKB:750100 ps, posedge CLKA &&& clka_enable:750100 ps, 100 ps ); # Time: 750100 ps Iteration: 1 Instance: /fifoctlr_cc_Testbench_Top/fifoctlr_cc_Inst/bram1 . . . . .

The application note doesn't say that fifoctlr_cc.v cannot handle simultaneous read/write, so I am not sure why these error messages get displayed. Eventually I ran out of ideas, so I decided to try ISE 5.1's Unisim library, and somehow this time the both FIFOs functioned correctly. Am I doing something I am not supposed to do with Virtex's Block RAM, or did Unisim's Virtex Block RAM contained a bug until the release of ISE

Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.)