Simulating TFT core in EDK

I'm trying to use the TFT IP core provided by Xilinx and am unable to simulate the entire system using ModelSim 6.1e. I've compiled the EDK and ISE libraries correctly, and I'm simply trying to find a way to let my verilog files know where to find the necessary files. When compiling the TFT piece, I receive the following error messages:

# ** Error: (vsim-3033) C:/vga_dcr_ddr/pcores/plb_tft_cntlr_ref_v1_00_d/hdl/verilog/plb_tft_cntlr_ref.v(501): Instantiation of 'BUFG' failed. The design unit was not found. # Region: /system/vga_framebuffer/vga_framebuffer/BUFG_pixclk # Searched libraries: # plb_tft_cntlr_ref_v1_00_d # ** Error: (vsim-3033) C:/vga_dcr_ddr/pcores/plb_tft_cntlr_ref_v1_00_d/hdl/verilog/plb_tft_cntlr_ref.v(526): Instantiation of 'DCM' failed. The design unit was not found. # Region: /system/vga_framebuffer/vga_framebuffer/DCM_pixclk # Searched libraries: # plb_tft_cntlr_ref_v1_00_d

The only thing I can think to do would be to copy the BUFG and DCM components from the ISE library into the simulation directory so that the compiler can find them. But, in order to do that, I think I need to modify the _info file that sits in the root directory to indicate that those files are there.

Are there any other steps that I'm missing?

Reply to
Jon
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Are you including the unisims directory in the verilog simulation with a -y option? You need to tell Verilog where the models for the BUFG and the DCM live.

John Providenza

Reply to
johnp

I'm assuming by that I need to put the -y option in the system.do file that gets generated by the EDK...

If so, I'll try it and see what I can come up with. Thanks.

Reply to
Jon

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