Hi alls,
I've a amazing problem in my virtex XC2V1000 design.
I've verilog code which normaly should generate a D flipFlop with preload ( and it did in functional simulation): input [7:0] reset; input [7:0] n_set; input [7:0] d; input clockIn; output [7:0] out;
reg [7:0] out_reg; wire [7:0] out = out_reg; wire trigSig = |(reset | ~(n_set)); always@(posedge clockIn or posedge trigSig) begin if(trigSig) out_reg = ~reset; else out_reg = d; end
The problem append when I use post translate simulation model ( based on simprims ) after synthesize my design with ISE 9.1i It seems my Flipflop has been convert to a latch : out_reg copy the d value during clockIn high state and block it during low state. So I verify which primitive was instantiate in the post translate simulation model generated by ISE, and I found a X_FF which is a flipflop... So I don't understand anything.. It looks very strange.. :- (
For information, I simulate with Cadence NC-verilog and NC-sim and I join simprims directory to my project to have Xilinx primitives.
If anyone could help me, because I haven't more ideas about what append..
Thanks by advance, best regards, Michel Talon.