I am just wondering if i simulate a design given in verilog using a test fixure in a modern simulator like ModelSim and the outputs are verified, what are the chances that the design will still not work in the actual FPGA assuming it fits and Place and Route is successful.
What are the factors that make this difference and how can i catch them in the design cycle.
I am actually creating few designs for DSP algos for my acadmic project, and being a beginnner in this whole DSP over FPGA I find it rather difficult to decide wather to call a successful simulation a milestone in the design cycle or not.
Assuming the test bench is at least mildly exhaustive (and why would you bother if it wasn't?), successful simulation is most definitely a milestone out in the real world. It lets you know not only that the high level architecture of the design is sound, but also that the logic being used to implement the design is mostly correct.
Lastly, if (or rather, when) a bug is discovered in the lab that the simulation didn't catch, you can go back to the simulation and increase your coverage, looking for other problems in addition to the one that was found in the lab. Then when the bug is seen in simulation, you can fix it, resimulate, and verify that you haven't broken some other part of the design, or uncovered another bug that was hiding behind that one.
The toughest part is simulating unforseen and sometimes hard to reproduce interactions with other devices outside the FPGA. But even in those cases, it is an invaluable tool. It is also usually considerably faster to debug with than running through the place and route tools.
To answer your first question, if the design meets timing as well as input and output constraints, and the the designer follows FPGA design guidelines (most important one: using global clock nets and no gated clocks), the chances are very high that the design won't fall flat on its face the first time it is put in a device. If I had to guess the most common trouble spot that people don't catch in simulations, it would be clock domain crossing problems - unless they used a FIFO.
In general, if the simulation says it works, it will work. Things that cause this to fail are:
1) synthesis didn't translate the design correctly. I've seen this on several occasions using XST, and I've also seen problems in the past with Design Compiler on ASIC projects. Synthesizers are made by people, so they have bugs too. Not too many, not often, but it does happen.
2) the HDL code has non-synthesizeable constructs, so it simulates fine but can't be "translated" into gates.
3) improper P&R constraints are applied, so the design can't operate at the desired frequency or else has odd setup/hold problems that show up when you least expect them.
4) design bugs that don't show up in simulation. This is probably the most common case. Maybe the testbench didn't exersize a section of logic. More difficult are clock-domain crossing problems that lead to metastable type problems. Clock crossing can also cause a variety of problems as you try to move data between clock domains. This is a topic in itself and, as far as I know, cannot be successfully simulated. For this class of problem, you have to make the design 'correct by design'. Clock crossing problems have been discussed in this forum many times, look for "metastable" as a good starting point.
With good simulation, I'd call passing simulation a milestone!
One thing simulation isn't good at is creating random inputs..for example... I've been working on a telephone port.. and the FPGA simulation is good.. but there are other chips, and they didn't always function as expected. This caused the real FPGA to lock up or and do strange, unexpected things also (accidentally) pins weren't locked down by the original designer so some features were by accident rather than by design.
The simulator also won't pick up metastability issues... I had that one byte me too
But a successful simulation is a milestone. I've taken a simulation to a working prototype PCB in less than a week.. Mind you .... I've spent the last 2 weeks fixing up "unexpected" glitches.. not to do with the FPGA.. but due to real world timings when the FPGA interacts with the outside world but the board did work exactly as expected.
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