I am doing my first FPGA design. The design uses VHDL source with a few Xilinx cores (a Virtex-4 device will be used). One of the cores is block memory used as ROM. The design does not use an embedded processor; the memory is addressed using a counter. My problem is that I don't know how to simulate the ROM. I have searched the Xilinx website and Xilinx help. I am using the latest Xilinx ISE and Active- HDL with all of the Xilinx simulation libraries furnished with the simulator. I want to do a functional simulation of the design using the ROM loaded with the code that will be used in the completed design. The design synthesizes with no errors and compiles OK in Active-HDL. I have made the .coe file for the ROM. I don't know what to do next to simulate the design incorporating the ROM. I can simulate it using a VHDL model of the ROM that I designed, but that does not give me a good feeling that the actual block ROM will work correctly.
I will appreciate any advice on this.