I have been reading through UG331 for information on the DCM, especially in the case with external clock feedback. On a previous project we used a Microblaze with an SDRAM controller, but did not have the external feedback. On this project, I have the board designers giving me a feedback clock path so I can deskew the SDRAM signals with a DCM.
The basic setup is (forgive the ASCII art; you probably need a fixed font to see it correctly):
+-----------------+ +------------------+ +-------+ clk -->| CLKIN CLK90 |-+--->| CLKIN CLK0 |--->|> | | DCM | | | DCM | | DDR Q|--| | | +-----------------+ | | +------------------+ +-------
- | | | | | +----------------------+
This follows the recommendation on p. 7 of DS492 (the MC OPB SDRAM Controller) in the EDK. The addition of the DDR register was a suggestion from our FAE and follows the recommendation on p. 111 of UG331. The DDR register is packed into the I/O and gives a clean, sharp clock signal.
The issue is how to reset the second DCM appropriately to make sure it locks onto a clean signal. I understand the need for the SRL16, so that the SDRAM DCM can get a clean lock. However, on p. 101 of UG331, Figure 3-19 shows the clock to the SRL16 being connected to CLKIN. At high speeds (100MHz or so) it only takes 160ns for the SRL16 to clear out. This means from the time from the end of the startup sequence to GTS deasserting must be less than 160ns. However, I cannot find any reference to the actual time from DCM startup to GTS deassertion.
It seems to me that the SRL16 in Figure 3-19 should be clocked by the feedback clock. This way the reset pulse occurs after the feedback clock is present, which is after GTS deasserts.
Any thoughts?