I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm told the jitter on the DCM output clock is likely to degrade the ADC performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I need 7x in the DCM.
Is the jitter really a major problem at 56MHz?
Thanks, Clark
That depends upon YOUR application.
Get out an old envelope and do some rough calculations.
What's the fastest rise time of a signal you will be looking at? As an estimate, use the highest frequency sine wave at max amplitude.
How many pico-seconds does your clock need to be off in order to make a 1 LSB change in the reading?
-- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Last time I checked, the jitter when using the CLKFX output was surprisingly large. I needed to multiply by 4X so I cascaded two DCMs together, using the CLK2X outputs, which had much less jitter. I don't know if CLKFX jitter has been improved since I last checked.
-Kevin
I'm
--
--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
The DCM won't work with an input frequency of 8MHz. The minimum input is somewhere around 24MHz.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian
To send private email:
0_0_0_0 snipped-for-privacy@pacbell.net where "0_0_0_0_" = "martineu"
FCS, how many times does someone say this on here? If you use the CLKFX output you can use input frequencies down to 1MHz, as long as the output frequency is over 24MHz. The OP's system will work, but it'll be jittery. Use the jitter calculator on the Xilinx website to find out how jittery. cheers, Symsx.>
Right you are. I assumed a couple of things here. One, that he needed this
8MHz input clock for the rest of the logic. Of course, you could use more than one DCM. No problems there.Jitter for a CLKFX-only implementation is about 0.9ns from 8MHz to 56MHz. This would affect the SNR performance (due to aperture uncertainty) attainable by an otherwise good ADC. I assumed that this would not be acceptable and, therefore, the CLKFX option would not be available. I would choose to go with a high quality 56MHz clock and divide it down for internal FPGA logic, if required.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
this
would
internal
Martin, Good points, your suggestion of using a good 56MHz source and a divided down enable for the 8 MHz functionality is the way I'd go too. Cheers, Syms.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.