Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"

Hi, I would like to use the Xilinx Spartan 3 DCI series source termination feature but the SSO guidelines from Pg25 of "DC and Switching Characterisics"(from the datasheet) leaves me thinking DCI is not supported for my IO standard and package.

The IO standard is LVDCI_33. I.e. I want to use series termination for

3.3V LVCMOS signals. The part we are considering is XC3S50 TQ144. The table on pg25 shows a "-" for the number of SSO (simultaneously switching outputs) for LVDCI_33. Does this "-" mean 0 are supported, or it hasn't been characterised yet, or ??

Questions:

1) Is LVDCI_33 supported for the TQFP144 package?

Also would be interested to know why it isn't supported.(extra pin inductance of the leaded packages??)

Regards Andrew

Reply to
Andrew FPGA
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Andrew,

Don't know, but I'll find out when I get back into work tomorrow (Memorial Day tody in US).

Aust> Hi,

Reply to
austin

The TQ144 package is one of the worst packages for SSO. In the datasheet I happened to check (v1.4) there is a figure for LVDCI_33 although the TQ144 is not listed in the table heading. There are VRP and VRN connections there on the TQ144 to support DCI so I can only think that it will work to some extent.

Generally mixing very high speed I/O and the TQ144 package is not good practise. If your I/O operates at lower speeds then setting the current drive on outputs to a lower value amy give nearly as good results as the DCI. Also does not increase the power consumption, and heat, like the DCI does.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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Reply to
John Adair

Hi John, Thanks for your points, yes indeed we have chosen the TQ144 package for cost reasons at the expense of performance. In our application we generate a few clocks at 2 and 4 MHz. As standard practice I was going to series source terminate these clocks output from the FPGA. I was aware of the Spartan 3 DCI feature, so I thought it would be nice to make use of it to remove these resistors off the PCB.

It would seem that I should do some IBIS simulations to show that reducing drive strength may allow me to remove the series source terminations completly? (I know there have been several posts in the past on how to do this). However, because of time constraints though I will stay in the 'dark ages' and just fit the series terminators to the PCB anway.

I would be interested to know why the TQ144 package has a "-" for LVDCI_33 though?

Regards Andrew

John Adair wrote:

Reply to
Andrew FPGA

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