Altera, Cyclone III, PCI, LVCMOS, & 3.3V

Some of my colleagues have designed complex PC type controller boards (PCI interfaces) where many different voltages are needed. In these cases, a complex switching power supply design is utilized and deriving one more voltage isn't too much of an issue.

By the way, there were a couple of recent discussions on this newsgroup about this topic titled, "Cyclone 3 on chip termination" and "Cyclone 3 margins: none at all at 3.3v"

For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for normal LVTTL type interface you can use 3.3V, I've done it. You just have to make darn sure that your transmission lines are designed properly.

Take care, Rob

bob elk> Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for

PCI, with Cyclone 3 parts ?

understand this apnote to suggest that any/all 3.3V

termination. (Assumptions for my design: 3.3V VCCIO on the

time)

rather than straight 3.3V LVTTL and LVCMOS, because the

easy to waive off, as I'm not designing an open PCI

requiring a new and unique supply voltage for all

are there any other options? External Schottky clamp

the bus ?

Then there's the due diligence work to ensure there

devices (e.g. what supply do you use for pullup resistors

the bird of Altera Paradise lands on my head to soothe

in this newsgroup!

Some of my colleagues have designed complex PC type controller boards (PCI interfaces) where many different voltages are needed. In these cases, a complex switching power supply design is utilized and deriving one more voltage isn't too much of an issue.

By the way, there were a couple of recent discussions on this newsgroup about this topic titled, "Cyclone 3 on chip termination" and "Cyclone 3 margins: none at all at 3.3v"

For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for normal LVTTL type interface you can use 3.3V, I've done it. You just have to make darn sure that your transmission lines are designed properly.

Take care, Rob

bob elk> Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for

PCI, with Cyclone 3 parts ?

understand this apnote to suggest that any/all 3.3V

termination. (Assumptions for my design: 3.3V VCCIO on the

time)

rather than straight 3.3V LVTTL and LVCMOS, because the

easy to waive off, as I'm not designing an open PCI

requiring a new and unique supply voltage for all

are there any other options? External Schottky clamp

the bus ?

Then there's the due diligence work to ensure there

devices (e.g. what supply do you use for pullup resistors

the bird of Altera Paradise lands on my head to soothe

in this newsgroup!

LVTTL type interface you can use 3.3V, I've done

properly.

Rob, what's the difference between PCI and 3.3V LVTTL, that one requires 3.0V and the other does not ?

- Bob Elkind

I've never personally designed with PCI but Austin made note in the previous discussion that:

"PCI at 3.3V REQUIRES reflective wave switching. That means the inputs have overshoot and undershoot BY DESIGN."

Rob

bob elk> ...

LVTTL type interface you can use 3.3V, I've done

designed properly.

and the other does not ?

And that should be fine as long as the overshoot falls within the acceptable range of the FPGA such as that defined by the Altera Cyclone III Device Datasheet: DC and Switching Characteristics, table 1-2, right? Big table, second page, hard to miss (at least for some readers).

There's an added advantage for modern CMOS drivers that are actively driving the line: not only does the PCI clamp help out but the driver actively pulls reflections back *down* to the positive rail when driving logic high; FETs are bidirectional, after all, and the IBIS models show the data to support this.

It's the non-driving FPGA I/Os that are subject to the reflective wave that are under the greatest stress. Even then, however, short PCI busses don't overdrive long enough to create problems for many lower speed signals like PCI. Add other devices along the path and you have other PCI clamps adding together to tame the reflections.

I'd appreciate any feedback on this perspective. Engineering discussions often fall on deaf ears when application notes or data sheets say "don't do this" even though it's followed with "unless you perform due diligence."

- John_H