Xilinx DCI resistor placement guidelines

Hi, I have been unable to find any info/guidelines for PCB placement of the DCI reference resistors. I.e. the resistors that attach to VRN and VRP. My instinct says decoupling capacitors highest priority (closest to FPGA package), DCI resistors next priority, and everything else lowest priority.

How senstive to noise are the VRP/VRN inputs?

FPGA is XC3S200-4FT256 and I'm using 49R9 DCI reference resistors.

Regards Andrew

Reply to
Andrew FPGA
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Great resource for decoupling cap placement and component priorities:

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According to this power distribution app note, page 12, placement of termination resistors takes precedence over decoupling caps. The DCI reference resistors function like termination resistors.

I have designed four different working boards using Virtex II Pro and/or Virtex 4 chips, and always put the DCI resistors closest to the FPGA on the ball layer. I can usually squeeze in a bunch of 0.01uF

0402 caps in the first ring around the FPGA perimeter on the ball layer. More 0.01uF caps on the bottom layer. Next ring has 0.1uF caps on ball and bottom layers, etc.

I always use side vias to power and gnd planes on my decoupling caps (Page 6) to minimize inductance. Never have room for two vias per cap lead (Fig 6D).

Do a search on "DCI" in the Xilinx Answers database for more info.

Hope this is helpful.

Reply to
mr_dsp

All,

Placement close to the chip is preferred, but since the ratio is 1:1, 1:

1:1/2 or 1:2 (ie a 50 ohm resistor can be used for a 25 ohm drive strength, or a split 100 ohm termination for 50 ohms), the impedance is low enough that coupling to the pin and causing it to not terminate correctly is unlikely.

There are DCI resistors for other companies chips which use a 10:1 ratio, so a 500 ohm resistor is used for a 50 ohm termination. One must be much more concerned with those resistors (as they are 10 times easier to couple to).

I would not put the resistor ahead of where a bypass capacitor would go, (bypassing is more important IMHO), but I would place it within 2 to 3" of the device, and I would not place strongly switching traces immediately adjacent to that 2 to 3" trace! I typically use a 3X spacing rule for reference resistors (and reference voltage pins), so that the trace to these pins has 3 times the normal spacing between traces to them. That takes the cross coupling to 1/9 a normally spaced pair of traces, which should be sufficient (but you should check anyway!).

Aust> >

Reply to
Austin Lesea

I don't think that this is the case. These resistors are not terminating a trace in any conventional sense; instead, they're acting as half of a resistive divider, the other half consisting of the N-channel or P-channel transistors inside the FPGA. The DCI cal circuit is looking at the voltage level on the DCI reference pin when the cal driver is on, to get an idea of whether the driver is higher or lower than the required impedance. It adjusts the driver impedance up or down based on the voltage it sees.

I certainly wouldn't put these resistors too far away; you don't want noise coupling into the traces when the FPGA is trying to make a calibration measurement. But the distance shouldn't be super-critical, either.

Bob Perlman Cambrian Design Works

Reply to
Bob Perlman

Thank you for the comments guys, it would appear they confirm my intuition.

Reply to
Andrew FPGA

If I'm not mistaken, you have the option of determining whether the "calibration" works once at configuration, or continuously during/after configuration. Continuous calibration compensates for temperature/voltage variances during operation, but other than that, it has no real advantages, and if the board is quieter at configuration, it might be helpful to select calibration at config only. IIRC, one-time calibration uses less power too.

If the calibration process is reasonably slow, is it possible to use a cap in parallel with the DCI resistor to help lower the AC impedance, and therefore reduce noise? (assuming noise was an issue in the first place)

In any case, I would not place DCI resistors close to the FPGA at the expense of bypass cap placement near the FPGA.

Andy

Reply to
Andy

Andy,

Do not place a cap in parallel with the DCI resistor.

If you do not need continuous calibration, then by setting it to calibrate once, you would need not be concerned about any noise.

Austin

Andy wrote:

Reply to
Austin Lesea

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