Does anyone have any good numbers for the power consumption used by the DCI circuitry on the I/O's? The data sheet says, and I quote, "more power". I kid you not--look it up.
There is a bit more info in a solution record:
But this looks like they came up with the numbers the same way I did in my lab. I would expect Xilinx to know this information since they designed the chip and be able to give some bounds on this number and some equations as to how to calculate it. Anyone can measure the extra current with DCI enabled and disabled as I did.
BTW, I measured 400mA more current on the 2.5V rail when DCI was enabled as to when it wasn't. I have 7 receivers spread over 3 banks.