Xilinx Spartan 3 DCI Power Consumption

Hello everyone,

Does anyone have any good numbers for the power consumption used by the DCI circuitry on the I/O's? The data sheet says, and I quote, "more power". I kid you not--look it up.

There is a bit more info in a solution record:

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But this looks like they came up with the numbers the same way I did in my lab. I would expect Xilinx to know this information since they designed the chip and be able to give some bounds on this number and some equations as to how to calculate it. Anyone can measure the extra current with DCI enabled and disabled as I did.

BTW, I measured 400mA more current on the 2.5V rail when DCI was enabled as to when it wasn't. I have 7 receivers spread over 3 banks.


Reply to
James Morrison
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I've posted a few links below to old posts on this subject for both V2 and S3.

It's particularly bad for the parallel input terminators, which have a +/-20% accuracy for the 2R pullup/pulldowns.

In V2, I measured static DCI power at about 200 mW per bank and 100 mW per LVDS_25_DCI pair (2.5V, 50 ohm VRP/N), much greater than the 25 mW and 62.5 mW numbers from Xilinx.

Back in early 2003, I opened webcases and filed CR's for the various tool and documentation problems relating to the greatly under-reported static DCI power in V2.

After a three month webcase, and countless phone calls and emails, the best Xilinx could do was give me an estimate, because they had never properly characterized DCI power after implementing the FreezeDCI bitgen patch.

After six months, the documentation and tools still were wrong, so I posted a summary of the various V2 DCI problems here in Fall 2003.

If you look today, 2.5 years post-Webcase:

Answer Record #11661 : ignores +/- 20% parallel terminator error, skips LVDS_25_DCI

Answer Record #15633 : still says 62.5 mW per LVDS_25_DCI pair

Answer Record #11794 : ignores stall-internal-resistor-at-R/2 case for VRP/VRN overhead

WebPower now includes LVDS_25_DCI for V2 and S3, but still under-reports power.

old DCI power posts:

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Reply to
Brian Davis

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