Spartan 3 termination question (DCI)

Dan,

Simulate it.

I doubt seriously that picking off the signal before or after a resistor at the receiver will make any difference at all (after all, the receiver has nearly infinite input impedance, and about 7-8 pF of capacitive loading, so what does a 82 ohm resistor to a 7 pF cap look like? not much I assure you).

As for setting the DCI resistance, use 82 ohm, or 33 ohm reference resistors to set the DCI series drive impedance to 82 or 33 ohms.

I would simulate it in Hyperlynx using the various IBIS models fromt he different vendors to prove that it works with high and low Vcc, and with fast and slow process corners.

A standard is a starting point. Either meet it exactly, and not worry, or simulate what you waht to do differently to prove it will always work the way you intend it to.

Your choice. By the way, I even simulate a standard interface, as I do not trust that the standard's body could anticipate every possible use of their precious standard, or that every vendor really 'met' the standard when combined with the other vendors in the design.

Aust> I'm looking at the DCI (digitally controlled impedance) part of the

Dan, when you use series termination on a unidirectional line with one driver and one receiver (the normal application), then you only series-terminate the driver, and there should be no resistor at the receiving end. The idea is to match the driving end, send a half-amplitude signal down the line, and make it bounce up to full strength at the unterminated receiver. Series termination takes advantage of reflection, unstead of fighting it. DCI is a nice way to manipulate the drive strength such that it matches the line impedance.

Peter Alfke, Xilinx Applications

Also works for a bidirectional line if you put series resistors at both ends. The one at the receiver doesn't get in the way. (At least not much and/or at speeds where you are likely to be using bidirectional lines.)

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Hyperlynx seemed like a good tool, but IIRC it didn't handle cables and connectors very well.

The best thing you can do on an ATA interface besides all the resistors is to use the 80 conductor ultra-ATA cables. The extra return lines really help. Obviously keep the ATA cable as short as possible. If you can only put one device on the cable at the far end. The ATA standard termination scheme is really ad-hoc, it was never really addressed until the standard started to push the speed envelope.

As for the DCI it does work, but my experience it's a real power hog. We had a 64-bit DDR interface and turned it on for a trial, and what used to be only a moderately warm FPGA turned into a burn-your-finger cooker.

Andrew,

DCI series termination does not draw any significant power. Only the parallel terminations are power hungry. Just because the resitances are on chip rather than off chip does not mean that there is no power dissipated: there is. Same power as if the resistors where off chip.

Aust> >

Let's squash an urban legend: In its normal use as series terminator, DCI shows insignificant additional power dissipation ( and zero additional system power compared to external resistors). It is only when DCI is used as parallel termination that it draws a continuous current and thus dissipates significant power. Peter Alfke

A bit more than zero power is needed for Virtex 2 DCI when you include the worst case VRP/VRN overhead power of ~200 mW/bank.

Should be much better in V2Pro and S3 with the new DCI control logic to cleanly stop the DCI updates.

Brian

Or maybe not- according to the following Answer Record, there's a 60 mA per bank hit when using LVDCI_33 in a Spartan 3, so the ~200 mW per bank number still applies.

I'm not sure why it's still so high, as I thought the main cause of the high overhead with the V2 DCI was that the FreezeDCI option randomly stopped the DCI update logic at whatever state it was in, possibly in an active R/2 matching mode, rather than cleanly stopping it with VRP/VRN inactive.

Answer Record #19628 Spartan-3 - How does DCI affect power consumption?

"In an experiment performed to test current consumption when using LVDCI, Xilinx found that for every bank that turned on DCI, the device consumed an extra 60 mA of current"

Brian

Brian,

LVDCI_33 is 60 mA for the reference resistors. For the whole bank.

Wow. Sooooo much current! Face it: setting the reference for the entire bank does take some power (in this case 3.3V X 60 mA or 200 milliwatts. I am pretty sure this is not going to "break the bank."

Yes, and if you just had to have all 8 banks use DCI, that would be 8 times as much current. I suggest that you confine the DCI interfaces to those banks that need them, not just for the 200 milliwatts.

Freeze DCI has nothing to do with it. The DCI circuit has to solve for

1/2 R, R and 2R, so the average current consumption is higher than it would be for R alone.

One trick you can use to cut it in half is to use 100 ohm reference resistors, and use LVDCI_DV2 (divide by two) to get 50 ohm drive.

Now you have 100 milliwatts dissipated for the feature of using DCI in the bank.

If you are thinking "why did they not use 10X reference resistors? (to lower power per bank)" the answer is very simple: the noise in a typical system would trash a higher impedance reference system, and the feature would have to be abandoned (or fixed) -- sound familiar?. From the first appearance of DCI in Virtex II, it has been a solid feature in every device since.

DCI updating is only an issue when you cross between two banks, and even then only with the parallel interfaces where it adds some small amount of jitter. Freezing the updates allowed customers who did not read that they should not go across banks to modify the bitstream, rather than re-design their pcbs. It also allowed the highest speed interfaces to have more timing margin (budget) which makes memory interfacing easier.

It is always preferable to provide the customer with solutions that involve changing bits, rather than making new boards (and them failing to place the orders that we desire). Now we have three different DCI options: regular (runs all the time changing +/- one trim), changes only when reguired, and "frozen" after matching (at configuration time).

Aust> Yesterday I wrote:

Austin,

Save your sarcasm for an instance in which it is merited.

Peter's claim of "zero additional system power" was inaccurate, especially coming after the "urban legend" lead-in.

If he has a problem with me pointing out the per bank overhead of DCI for V2 and S3 parts, I'm sure he'll speak up about it.

In a small Spartan3 design drawing little current on VCCINT, power consumption would be dominated by "sooooo much current", especially if using 33 ohm VRP/N resistors as you suggested earlier in the thread.

It would be much better to shut down the VRP/VRN outputs after configuration when DCIUpdateMode=Quiet, which would eliminate the DCI power overhead completely for series DCI.

When last I checked in detail (Fall 2003), all of Xilinx's power estimation tools, published data, and Answer Records failed to properly report static DCI supply current, for both per-bank overhead and per-input parallel termination.

As for the rest of your post, I could point out in detail the various errors and omissions you've made, but I don't have the time or patience tonight to explain things that should have been properly documented in the Virtex2 application notes and datasheets long ago.

Brian

Brian,

I would appreciate it if you did detail every single omission, distortion, or mis-representation.

In fact, I demand it, or an apology. As you know, when I make a mistake, I own up to it immediately. I expect no less from others.

To say "if you are already drawing no power, then 200 mW is a lot of power" is a pretty inane response.

Obviously. Your point?

Peter's comment is perfectly accurate: series terminations dissipate virtually no power in the series termination resistors.

As for my sarcasm, although sarcasm is known as the "weapon of the weak." it does serve a purpose to emphasize a point. I reserve the right to be as entertaining as possible.

Thanks for the suggestion of turning the reference resistors off. Not a bad idea at all.

Power estimation tools lag the rest of the tools. Entering in the omissions on the hotline generates corrective action reports, which gets them fixed. I will check to see where we are.

Austin

Austin,

Where did you get your incredible attitude? I normally refrain from posting about your mildly offensive posts, but when you call others on the carpet like this it is just too much.

Your sarcasm added *nothing* to your message. It simply made you look silly and as you said, "weak".

"Wow. Sooooo much current!"

REALLY! This makes you sound like a 12 year old in the school yard... nothing entertaining about that!

Your posts are normally useful and informative. Just leave the attitude out of it, ok?

Aust>

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Rick,

Bad sleepless night. But really, I was offended by the silly response, talking about applications that have 'no power' where DCI is all of the power.

Let's face it, I can create any example I want (the part is programmable after all).

So I can 'prove' that any current is either a major issue, and can not be tolerated whatsoever, or than it is totally insignificant.

That was the point of my 'school yard' comment.

Sorry to have offended you.

I have so many friends out there, I was actually surprised when no one called me on that one.....they call me on just about everything else!

Austin

At least you realized that you were going off a bit. The bad ones think they are totally justified. :)

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Rick,

I am really so easy. I recognized a long time ago that most engineers are insufferable prima donnas, with egos that encompass small planetary systems....

Thus, if I can not nurture my idiosyncracies, I would not have any personality at all....

Aust> Aust>

( reposting this, as the first try never showed up )

Austin,

Responding slightly out of order:

It's much more preferable to provide the customer with a DCI adjustment circuit which doesn't glitch the impedance so much when updating, and require years of subsequent BitGen tweaking.

You even said as much yourself, over on this thread in 2001:

Wherein you stated that the magnitude of the DCI impedance updates was insignificant.

In that same thread, you also suggested that there was only a 25mW power hit for each VRP/VRN pair:

Would you care to update either of those claims for Virtex2 ?

Coming soon to a newsgroup near you...

The only apologies due here are:

- from Xilinx, to its' customers, for failing to properly document the plethora of Virtex2 DCI HW and SW problems, now at 3.5 years after V2 product launch and counting.

- from you, for posting another sarcastic, condescending, and disingenuous response to an accurate and level-headed post

Inane, huh? I found my original sentence quite pithy when contrasted to your three paragraph "Nobody cares about 2 W per chip" denial.

Just how much power do you think a

And what, pray tell, does that have to do with my statement:

'Peter's claim of "zero additional system power" was inaccurate' In Austin's world, has the term "system power" been explicitly redefined to exclude per-bank DCI overhead?

Brian

(snip)

See:

He has a challenge to build computers using one millionth of the power of current systems, so maybe 100 microwatts.

On that scale, 200mW does break the bank.

There are people interested in micropower logic.

-- glen

Glen,

I'm impressed. A million to one reduction in current?

Did anyone hear how he accomplished this miracle?

Austin

Modern high-performance sub-150 nm conventional CMOS technology has leakage currents that make that goal unattainable (by a long shot). Such a requirement is not mainstream... Peter Alfke ============================