Xilinx ISE Webpack - Any usable simulator for the Linux platform ?

I am very happy with ghdl, i almost use only that. Also for the post trans/map/p&r simulations.

Laurent Pinchart ha scritto:

Hi Antonio,

Does it work with Xilinx cores/primitives ? Do you know of any howto that describes how to setup a Xilinx project (VHDL source files + core/primitives) for simulation with ghdl ?

Laurent Pinchart

Hi Laurent and Antonio,

I would like to provide a bit of information on ISE Simulator that may help solve the issue you encountered while using ISE Simulator.

ISE Simulator by default comes up with only the waveform of top level signals shown in the Wave Viewer. But, you can add additional signals later. Click on the tab named "Sim Hierarchy - " (you will find it adjacent to the "Processes" tab ) in the ISE after you have launched ISE Simulator. You can then expand hierarchy and see internal structure and signals. Then whichever signals you desire to add to Waveform Viewer, you can select them and drag them to Wave Viewer. You will see empty Waveform for newly added signals if they are not connected to the top, else you would see a waveform for the newly added signals.

Next, enter "restart" on the tcl console of ISE Simulator ( See tab "Sim Console - " in the bottom console window) or use Tool bar (

I haven't used it myself but other posters have commented favourably on Simili

It has a Linux version.

It's not free but it's also not that expensive.

Hope that helps,

Alan

Hi Kumar,

Thank you for your quick reply and the information you provided. Unfortunately, I still haven't been able to get any decent result from the Xilinx ISE Simulator.

My problem might come from the fact that I can't seem to launch the simulator at all. The only option I found to view the waveform is to double-click on the .tbw file in the Sources tab. The Hierarchy tab then only shows the top-level signals (ports).

When selecting the test bench file and double-clicking on "Simulate Behavioral Model" in the Processes tab, ISE starts the simulation process and outputs the following messages.

Running Fuse ... WARNING: en_GB.utf8 is not supported as a language. Using usenglish. WARNING: en_GB.utf8 is not supported as a language. Using usenglish. WARNING:HDLParsers:3215 - Unit work/pwm_test is now defined in a different file: was /home/laurent/src/motion/test/sim/pwm_test.ant, now is /home/laurent/src/motion/test/sim/pwm_test.vhw WARNING:HDLParsers:3215 - Unit work/pwm_test/testbench_arch is now defined in a different file: was /home/laurent/src/motion/test/sim/pwm_test.ant, now is /home/laurent/src/motion/test/sim/pwm_test.vhw Compiling vhdl file "/home/laurent/src/motion/test/sim/pwm_test.vhw" in Library work. Entity compiled. Entity (Architecture ) compiled. Parsing "pwm_test_beh.prj": 0.11 Codegen work/pwm_test: 0.00 Codegen work/pwm_test/testbench_arch: 0.01 Building pwm_test_isim_beh.exe

Nothing else happens, no simulator window appears.

The link "Launching Xilinx ISE Simulator" in

Regards,

Laurent Pinchart

Quartus FLOATLNX $3k license covers linux modelsim for vhdl or verilog. This would cover functional simulation, but probably no backanno for models other than Altera.

-- Mike Treseler