Hi,
i tried to simulate a small vhdl design with xilinx ISE (8.1 - 8.2 spxx, Webpack or foundation) running SuSE 10.1 linux, unfortunately there is an error. Because the VHDL code simulates with SuSE 9.2 I assume the code is fine and there are no spaces in the file path.
Started : "Check Syntax". Running vhpcomp Compiling vhdl file "/home/PBuser2/parity/parity.vhd" in Library isim_temp. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "/home/PBuser2/parity/tb_parity.vhd" in Library isim_temp. Entity compiled. Entity (Architecture ) compiled. Parsing "tb_parity_vhd_stx.prj": 0.03
Process "Check Syntax" completed successfully
Running Fuse ... Parsing "tb_parity_vhd_beh.prj": 0.00 Building tb_parity_vhd_isim_beh.exe ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
Has anybody simulated ISE isim under SuSE 10.1. Any hint is appreciated.
Andreas