A while ago Xilinx introduced the parameter "Tsamp" into the Virtex 4 data sheet, described as: "TSAMP Sampling Error at Receiver Pins This parameter indicates the total sampling error of Virtex-4 DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew."
This is a big help to people designing high speed source synchronous interfaces. Does anyone know if there is a similar characterisation for Spartan 3 (or any other parts, for that matter)? It does not appear in the data sheet, but there is a tantalising reference to it in ug2565.
It would be great to see it characterised for all parts. PS - I'm raising a webcase, but the process is proving a bit slow.. Nick