Xilinx ISE Simulator Arrays

The ISE 7.1i Simulator has trouble displaying the array in the code below. Specifically when the mem array is added to wave, and the + is clicked to explode the memory contents, the individual bytes are not segmented and what you see is the entire mem array as if you had not clicked the +.

Am I doing something wrong or is there a work around? The free ModelSim XE Starter has no issue here. This happens only with the ISE simulator.

Brad Smallridge Ai Vision

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mem is PORT ( clk : in std_logic; data : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0) );

end mem;

architecture Behavioral of mem is

TYPE memory_array IS ARRAY ( 0 TO 3 ) OF std_logic_vector(7 DOWNTO 0 ); signal mem: memory_array;

begin

process(clk) begin if clk'event and clk='1' then mem(0)

Reply to
Brad Smallridge
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My guess is since ModelSim is a pure simulator and not a synthesis tool, it will run simulation for your code as long as it is free from syntax error. ISE Simulator, on the other hand, demands that your circuit must be SYNTHESIZABLE, in addition of being syntactically correct. Your code is not synthesizable. It's missing something. What happens to mem(1) and mem(3) at every rising edge of the clock? You need to define that. If your tool doesn't like 2D array, try to think how would you make a

2D array in hardware and implement that in VHDL.

Hendra

Reply to
Hendra

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