Differences between Xilinx ISE and Altera Quartus software

Looks a good idea.

You could clarify that this is comparing FREE versions, with maybe the cost of the first step upward from that ?.

Perhaps a Device Ceiling (Part num and appx resource ) ? " Free up to XXXX "

Installed size (100's of MB ?), and machine minimums in MB RAM and GHz clocks....

If you can be bothered, Links to a small code snippet for VHDL, verilog, ABEL, AHDL could clarify that for beginners - something like a 4 bit U/D/LD counter ?

-jg

Jean Nicolle wrote: : Hi all,

: I tried to summarize the differences in a table. :

: Sorry about the link, it wasn't easy to duplicate the table in text form for : this posting.

: Things I'd be interesting to hear about: : 1. is the info accurate? : 2. did I miss important features that differentiate the 2 software? (without : getting into details, these are big software...)

: The table is intended as a beginner's guide to FPGA's software. : Thanks for any help/comments.

You can use Iverilog for Xilinx too. And Cver also for both. Cver alos knows about SDF and can be use for post layout simulation.

Bye

for

(without

I assume this is all for the Windows PC only. If so, what version(s) of the OS are supported - I believe Altera still supports Windows 98 and ME while Xilinx requires NT or XP. If not PC only, does it run on Linix? Not everybody, especially those doing things "for fun", have the latest OS versions. I ended up with Quartus because I'm still running 98SE.

Actually the table is intended for both.

Looks like the limit is 200KGates for Altera and 400KGates for Xilinx.

I'll look to see if there are big differences in the requirements. I could also include the OS'es supported

Sounds like a good idea.

knows

Sounds interesting. Here, right?

It doesn't seem available for free anymore though, even for non-commercial use.

Do anyone knows the price of ISE/Quartus? Do they come with the same scheme (1 year licencing)? Once the license expires, does the software stops working, or there is just no more updates?

Thanks.

Jean Nicolle wrote: : > You can use Iverilog for Xilinx too. And Cver also for both. Cver alos : knows : > about SDF and can be use for post layout simulation.

: Sounds interesting. : Here, right? :

: It doesn't seem available for free anymore though, even for non-commercial : use.

There's a GPL-Cver version

Thanks, that is great. A minor note : AHDL is standing for Altera Highlevel language. AFAIK, the free version only supports Megawizard function to be output in AHDL.

Some pricetags would help too. The license restrictions would also be of interest. AFAIK, the Quartus2 free license is 90 or 180 days.

Rene

Hi,

This is a correction to Rene's posting. The Quartus II 3.0 Web Edition license duration is for 180 days, and can be renewed as many times as needed from the web, i.e. there is no need to upgrade to a full subscription at the end of the 180 days. The Megawizard Plug IN Manager in the Quartus II 3.0 Web Edition provides output in VHDL, Verilog and AHDL.

- Subroto Datta Altera Corp.

There at least were NIOS kits, meaning some FPGA, Stratix, or Cyclone hardware together with a full license upgradeable withing a year to the latest version. At around 450$ they were a bargain, considering the hardware. You're never doing your own hardware for that little.

I wasn't able to run the kit due to configuration problems and lack of time. So I cannot comment any further yet.

Rene

Xilinx ISE Foundation

Petter

Cool, table updated with the prices.

cool, found it

Dear Altera Corp,

could you please also confirm is SOPC Builder that is bundled with Altera Quartus II 3.0 Web Edition useable at all or not.

so far all our attempts todo something with it have failed: NIOS is supplied (white icon?), after requesting NIOS evaluation license and installing it, nothing changes, the NIOS in SOPC is not enabled. and if there is no Avalon master then the SOPC doesnt do anything at all. SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from provider DCD) - unfortunatly there is some problem as per DCD on Altera side so DF6811 is not enabled in SOPC, so no way. No Processor enabled, no avalon master no system can be built :(

I dont get it - if SOPC is included in free edition there should be something that can be done with it ???

In previous versions of Altera free software I think the NIOS evaluation was possible, unfortunatly I had very little time then and now this older version probably would not recon the new license.

Ok, the long story short - is there any way to evaluate NIOS without paying up front ?

Thanks Antti Lukats altera.openchip.org

paying

hardware

version.

Well, yes, I know there are kits at different price tags, but Altera says on the website it is possible to evaluate NIOS without purchase (of NIOS or eval kit). And if some Feature is included in some some software (like SOPC Builder in Quartus Web Edition) then I guess it should be useable. So I am still hoping that I am so stupid and cant figure it out how it can be used. I started to write my own CPU for SOPC, but well it too much trouble just to see if SOPC Builder does something or not. Hope somebody can clear this up. In case SOPC Builder is useable in evaluation mode only with 3rd party processors (not NIOS) would be nice to know which ones are available and working (the first one we tried turned out non-SOPC Builder ready, despite its advertizing)

antti

Hi Antti (and anyone else interested in the above question),

A colleague of mine answered this on your openchip web forum:

PS: The "white dots" in SOPC Builder show components that are available elsewhere for download/CD, but not installed on your system. There is a CD coming out shortly with an eval version of Nios. It will be separate from the free Quartus download. Here is the link:

SOPC Builder is more of a design tool -- it did make its debut with Nios and remains the main tool in the HW portion of a Nios design, but there are many uses for it independent of Nios (for building interconnects between user logic, downloading SOPC Builder components from 3rd parties, using the Excalibur devices, etc.). This is why it is installed automatically with Quartus now.

Jesse Kempa Altera Corp. jkempa at altera dot com

Ummmmmmmmmmmm...the most obvious, and perhaps most important difference, is that Quartus only supports Altera parts, and Xilinx ISE supports only Xilinx parts.

In other words, you choose the device based on whatever parameters you care about, and then you get the software that lets you design the chip. If only a Xilinx device has a gotta-have feature, it doesn't matter if Altera's software is cheaper/better/gets-you-a-good-raise/gets-you-laid (all of which may or may not be true) because you can't use it for Xilinx parts.

The table is now part of the site, see

It looks fine except for functional/timing simulation.

Xilinx has MTI starter which is VHDL or Verilog, but only 500 lines of code. Altera has their own gate level simulator. Both have issues, but it is unfair to just say NO for Xilinx and YES for Altera.

Peter Alfke, Xil>