Hello group.
Regrettably, I just installed 7.1 in my computer in order to try the implementation of one of my designs in the SP3E and V4 chips. As a first test, I targeted it to the same XC3S100 device I was using in 6.3 in order to make some comparisons. After some minutes and to my dismay, I was surprised that my design doesn't fit in the XC3S100 any more! 6.3 synthesized the design perfectly in ~550 slices, but now 7.1 wants more than 900 slices for it. Implementation with the same constraints is also around 25MHz slower. I checked the synthesis report and the main difference is that MUXes went from 28 to 52 in a totally different arrangement:
6.3: # Multiplexers : 28 12-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 8 16-bit 4-to-1 multiplexer : 2 1-bit 2-to-1 multiplexer : 14 4-bit 2-to-1 multiplexer : 2 8-bit 2-to-1 multiplexer : 1
7.1: # 1-bit 4-to-1 multiplexer : 16 # 1-bit 8-to-1 multiplexer : 2 # 16-bit 4-to-1 multiplexer : 27 # 16-bit 8-to-1 multiplexer : 4 # 3-bit 4-to-1 multiplexer : 1 # 4-bit 4-to-1 multiplexer : 2
I am also getting the following PACKER Warning I had never heard before: "Lut X driving carry Y can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough". Does somebody has an explanation for this?
I can't believe things are so different. Maybe there are new "features" I am not aware of?
Regards.