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"The ISE 7.1 Experience"

Hello group.

Regrettably, I just installed 7.1 in my computer in order to try the implementation of one of my designs in the SP3E and V4 chips. As a first test, I targeted it to the same XC3S100 device I was using in 6.3 in order to make some comparisons. After some minutes and to my dismay, I was surprised that my design doesn't fit in the XC3S100 any more! 6.3 synthesized the design perfectly in ~550 slices, but now 7.1 wants more than 900 slices for it. Implementation with the same constraints is also around 25MHz slower. I checked the synthesis report and the main difference is that MUXes went from 28 to 52 in a totally different arrangement:

6.3: # Multiplexers : 28 12-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 8 16-bit 4-to-1 multiplexer : 2 1-bit 2-to-1 multiplexer : 14 4-bit 2-to-1 multiplexer : 2 8-bit 2-to-1 multiplexer : 1

7.1: # 1-bit 4-to-1 multiplexer : 16 # 1-bit 8-to-1 multiplexer : 2 # 16-bit 4-to-1 multiplexer : 27 # 16-bit 8-to-1 multiplexer : 4 # 3-bit 4-to-1 multiplexer : 1 # 4-bit 4-to-1 multiplexer : 2

I am also getting the following PACKER Warning I had never heard before: "Lut X driving carry Y can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough". Does somebody has an explanation for this?

I can't believe things are so different. Maybe there are new "features" I am not aware of?

Regards.

--
PabloBleyerKocik
 pablo          /"Reliable software must kill people reliably."
  @bleyer.org  / -- Andy Mickel
Reply to
Pablo Bleyer Kocik
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Pablo,

Have you logged this into the hotline as a case? Best way to address new software glitches is to report them.

It might be a bug, it might be a new feature.

Only way to find out is to look. You can help us just by logging it in.

Same amount of work as this email posting, maybe less.

Aust> Hello group.

Reply to
Austin Lesea

Yes, I am planning to do that. But first I wanted to ask here in case I was doing something terribly dummy (you know, embarrassment-concerning replies tend to be faster here). I will use the 6.3 installed in another computer to gather enough evidence and submit a full case report.

Thanks again. Cheers.

--
PabloBleyerKocik
 pablo          /"Reliable software must kill people reliably."
  @bleyer.org  / -- Andy Mickel
Reply to
Pablo Bleyer Kocik

There are plenty of issues in 7.1 SP1. Handle with care!

Alfred

"Pablo Bleyer Kocik" schrieb im Newsbeitrag news:d3k0an$15r$ snipped-for-privacy@domitilla.aioe.org...

was

tend

gather

Reply to
Ralf Duschef

Or, avoid them by using carefull regression testing before release ?

Wot No Smiley ? Please justify how a slower result, more slices, and an ultimate 'no fit' can possibly be called a 'new feature' ?!

Well, certainly less bad publicity/egg-on-face for Xilinx ?

-jg

Reply to
Jim Granville

yes, there are :-(

good advice - use it, but carefully

Aust> > > Have you logged this into the hotline as a case? Best way to

address

Hopefully, it's not only me, reporting 'glitches' (!?!) to Xilinx... Maybe SP2 has 'stabelized'.

b.t.w. - heard about 'glitches' only in HW-Design before !!!

Jochen

Reply to
Jochen

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