I use synplify 8.8 to synthesis my design. And my design contain xilinx ip core (generated by core generator). My design can be synthesis with XST. But when I use synplify 8.8, synthesis cannot be done successfully. It seems that synplify does recognise xilinx ip core.Do i need to set some option?
Thanks for your help!
In what way does Synplify not recognize the core that you added to your Synplify project?
Is it a Black Box wrapper that you added to the project?
Or is the core supplied as a Verilog or VHDL file rather than a black box wrapper for a pre-synthesized core that gets brought together in the back-end tool?
If you want to add Coregn cores there are a few choices:
- .edn netlist (fine for memories), Remark: only contains top level for other cores than memories. - .ngc. Please use ngc2edif.exe from ISE installation directory. Generates .ndf netlist which actually is EDIF. Add file to project.
You mentioned your design could not be synthesized successfully. Please be more precise what the problem is.
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