combining two EDF netlist in ISE

Hello guys,

I am working on a project which contain some IP core which is avaiable to me in EDF netlist form. I am having the following doubt I synthesis my verilog code in synplify and implementing this EDF in the ISE. Now since i have my design in EDF format , how can i instantiate a new IP core which in EDF format in my design which is also in EDF file.

Is there a way by which i can instantiate the netlist of IP core in by verilog code. If so how do i do that? waiting for your reply, Thanks and regards williams

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Make it a synthesis black box. The synthesis tool will put a placeholder for the undefined module and ISE should put appropriate EDIF file where applicable as long as the instantiated EDIF is stored in one of the macro search folders. Declare such module as follows:

module CBD16CE(CEO,TC,Q,C,CE,CLR) /* synthesis syn_black_box */; output CEO, TC; output [15:0] Q; input C, CE, CLR; endmodule

Aldec's Active-HDL has also an utility that allows to merge all HDL files in the design including EDIFs so you combine everything after synthesis and pass flat netlist to the place-and-route (usually faster).


Reply to
Engineering Guy

Make a dummy module with same interface in your HDL. Tell your synthesis tool that this is a black box. You can then merge the edif netlist in ngdbuild.


A: Because it messes up the order in which people normally read text.
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Reply to
Petter Gustad

The best thing to do is to add the lower level EDIF file as an input file in the Synplify Project. Synplify will then be able to use the contents of the EDIF file as a timing model and an interface spec. The timing model will help Synplify optimize the logic around the EDIF instantiation.

Ken McElva> Hello guys,

Reply to
Ken McElvain

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