I am working on a project which contain some IP core which is avaiable to me in EDF netlist form. I am having the following doubt I synthesis my verilog code in synplify and implementing this EDF in the ISE. Now since i have my design in EDF format , how can i instantiate a new IP core which in EDF format in my design which is also in EDF file.
Is there a way by which i can instantiate the netlist of IP core in by verilog code. If so how do i do that? waiting for your reply, Thanks and regards williams