Xilinx and Altera -- maximum total bitrate for high-speed serial I/O

Ian,

MGTs for V4 are 622 Mb/s to 10 Gb/s each. They are similar to the already shipped and working 10 Gb/s transcievers in Virtex II Pro-X.

They can be channel bonded together for even higher aggregate data rates.

Aust> I'm looking ahead to an application in the future which will need a

Hi Austin

Thanks for that -- I wasn't really sure that the Pro-X and V4 were

Of course 10Gb/s real data rate gets you into a whole new raft of issues with PCB/connectors/sockets because the edge rates are so fast

-- we've done boards with a small number of 10Gb/s channels where we had to take extreme care over things like via stubs and choice of layers. Maybe the best compromise here is 5-6Gb/s per channel, which would give half the number of channels compared to 2.5-3Gb/s, but be less critical physically than 10-12Gb/s.

Cheers

Ian

P.S. Anybody else out there have any enlightening comments on this?

Ian,

Well, I certainly understand that a speed bump to a 6 Gbs is more like a roadblock to a 10 Gbs signal. Until everything catches up (pcb technology, SI engineering) not going for 10 Gbs if you don't have to is probably a good idea. 6.25 Gbs is looking quite nice, as you say, given pcb and connector technologies.

And, yes, I am aware that most people mean 4 X 3.125 Gbs (using 8b10b) which yields an actual total aggregate bit rate of 10 Gbs when you say "10 Gbs channel."

Remember to divide by the coding scheme overhead to get the actual useful bit rate. (so even 10 Gbs using 8b/10b is less than 10 Gbs of useful data -- even though the bits do fly by at that 10 Gbs rate)

There is another coding scheme that is used at the higher rates, 64b66b, which is much more efficient (more useful bits than 8b10b). We support this coding scheme, too.

Austin

Ian Dedic wrote:

Ian, Stratix II GX will elevate LE count, increase transceiver speed, and increase channel count. I think the majority of chip-to-chip and backplane requirements in the next generation will be better addressed by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps range based on supporting infrastructure required. More details on Stratix II GX are available today with an NDA.

Dave Greenfield Altera Marketing

Thanks Dave -- it sounds like all our views agree here (see other mails in thread) that 5-6Gb/s as a next step avoids the issues which become difficult at 10-12Gb/s. Also given the number of channels available (from Altera and Xilinx) this will meet our requirement (up to about 100Gb/s total throughput).

Ian

Ian,

There is a definite advantage to using a transceiver designed to work at

Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them has to be just perfect, and pass the production BER test. We are in production. At 10 Gbs.

And, you can see (and get delivery of) the Pro-X transceivers (today at the many RocketLab(tm) demo sites we have around the world).

No "will", "more details under NDA", or any of that. Just product, working, on the shelf, shipping NOW.

Aust> Thanks Dave -- it sounds like all our views agree here (see other

Hi Austin

Obviously there is more margin if you're not pushing the transceiver so hard, and being in the IC business I always take "real-soon-now" with a large pinch of salt.

But in the timescales we're looking at it seems that there will be solutions from both the biggest FPGA vendors, which always helps when talking to customers who might exclusively use one or the other...:-)

Cheers

Ian

Aust> Ian,

Ian,

OK. Time is on your side if you can wait.

Aust> Hi Austin

I would not even consider using a high-speed I/O part unless I see it working for real on a board. And with some characterization data to back it up. That's because engineers have been burned too many times for claims of serial I/O greatness only to be left without working silicon when it comes times for the rubber to hit the road.

Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too critical to count on some powerpoint presentation that claims great I/O performance.

You can get a Xilinx V2 Pro X today and verify for yourself if it meets your needs in the lab. Real silicon operating at 10 Gbps on a real board. Case closed with no decision for me unless I can see a Stratix II running on a real board.

With Xilinx you don't even need to have all the great equipment yourself. You can go to a rocket lab and see for yourself.

Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25 Gbps device at 6.25 Gbps. I'll take all the extra margin any day.

Comments inserted inline...

Which is why I made the pinch of salt comment

Agreed 100% -- at the point when a hardware decision has to be made.

Or Stratix II GX (which doesn't exist yet). Xilinx undoubtedly have a technology lead now as far as CDR is concerned, so Altera will have to improve theirs. Very few applications need (or can cope with) 10Gb/s now (and using these rates in practice is not trivial) but many need

Given a free choice *and all other things being equal*, I'd agree. But...

Are you seriously suggesting that I go to a happy all-Altera customer and tell them that they'll have to switch over to Xilinx if they want to use our technology?

I can tell you what the outcome would be, and it wouldn't involve Xilinx...:-)

Ian

Ian,

Most customers are not stupid: if they see their competition using Xilinx, and beating them, they are unlikely to remain so fixated on a particular vendor.

I understand that there are Altera customers who are so committed, that they will not consider any other solution.

The oppsoite is true, as well.

I don't think we need to discuss it here. More intersting are folks who want the best features, performance, support, software, cores, and tools. And are willing to examine all vendors.

Those are the ones I want to reach.

By the way, there are customers who believe that in order to keep both vendors alive, they have to intentionally switch every so often.

Aust> Comments inserted inline...

Austin

Obviously if one vendor has an overriding advantage for a particular application then they'll be used -- so is somebody really needs an FPGA with 10Gb/s I/O now or in the near future they've got a choice of Brand X or Brand X...:-)

But if they're already using Brand A and it suits them and their engineers are familiar with the tools and so on, I don't want to have to tell them to switch.

If being the best always won we'd now be dumping Betamax video recorders for DVD rather than VHS, I'd probably be writing this on a Mac not a PC, and Bill Gates would be flipping burgers. If only...

Ian

aust> Ian,

Ian,

So it goes. Training on the tools and familiarity is a big cost, I know.

To decide to switch to another tool flow is often very painful, and expensive.

But, that should not be the reason to NOT consider another product. That is what having training courses (either on your site for larger audiences, or at 'Xilinx U') is all about.

We have trained entire departments of engineers to take advantage of our features.

Have fun,

Aust> Austin

Hi,

Without undermining Xilinx's achievements in the 10Gb/s space, I would like to point out that using a 6.25Gb/s tranceiver is better than a

There are several reasons:

1. A PLL designed for 622Mb/s to 10Gb/s has a wider tuning range than a PLL designed for up to 6.25Gb/s; hence, the performance (jitter) of a PLL designed up to 6.25Gb/s is better.

1. Using a 10Gb/s transceiver to run at 6.25Gb/s wastes area, power, and the customer has to pay a premium for a turbo-charged transceiver that he/she will not use at full-speed.

2. Moreover, your choice should not only be based on the transceiver. It is just part of the whole solution. FPGA core fabric should also be taken into account. Does the core fabric have enough LEs to process all the data coming in at 6.25Gb/s? A 10Gb/s transceiver may require more LEs, and if not used, will be wasted.

These are just a few reasons to choose a 6.25Gb/s transceiver.

BTW, there are 15+ FPGA/ASIC/IP/ASSP vendors who have 6.25Gb/s transceivers. This enables industry interoperability at 6.25Gb/s. It will be the sweet spot in the coming years.

Aside from these comments, the RocketIO group at Xilinx did an outstanding job on the 10Gb/s transceiver. However, the market crash in 2001 has pushed the standarization of 10Gb/s for many many years. Therefore, it is not unreasonable to say that it was over-engineered and customers will have to pay for this innovation even though they may not need it.

Zhi

This *can* be true if the PLL is designed for ONLY a tight frequency range. A 6.25 Gb transceiver will have no better PLL performance if it still requires greater than 1 octave of tuning. The generalization isn't valid.

Do you get the point about performance margin? If I need to drive 70mph and lower, I can get an economy car. I own something with a bit more spunk because it gives me headroom in performance. If you can keep your eyes open enough at 10 Gb, you can keep your eyes wide open at 6.25 Gb. The inverse is not true.

Is the area indeed greater? Can't the same SerDes functionality occupy the same space with good design? A 10 Gb channel run at 6.25 Gb will consume about 62.5% of the full speed power.

If the solution cost for 10 Gb transceivers is significantly greater than the 6.25 Gb solutions, the overall development cost has to be considered for board spins and time to market, design support and production quality. The

Again, running a 10 Gb transceiver at 6.25 Gb will use the same number of LEs as a 6.25 Gb transceiver running at 6.25 Gb.

Zhi,

I beg to differ.

See below,

Aust> Hi,

The PLL's are programmable. No way we could go from 622 Mbs to 10 Gbs with one PLL without changing something. The PLL is optimized for the bitrate you select.

Jitter is also optimized for the bitrate. A receiver that has a 10 Gbs bandwidth will be more capable of discerning edges at lower rates. Also a fact. This will lead to a wider eye opening, and better jitter performance.

It is true that running a 10 Gbs MGT at 10 GBs takes more power than at

Logic elements used are hardly used based on the MGT bit rate. The physical layer interface is hard coded in the FPGA, and ours has a multitude of features that saves logic element usage. Logic needed is what the customer needs to do their job. Bit rate is a separate issue from that altogether.

All the wrong reasons. Here is my list of reasons:

Anyone's guess, but I do not disagree. There is no accepted standard at this rate yet, however.

And, I never count IP providers without seeing their silicon first.

Right now, there is only one FPGA supplier with 6.25 Gbs capability: Xilinx.

Thanks.

Hmmm. I know the meetings are still being held, and folks are still fighting over the standard for 10 Gbs.......

The cost of the engineering of the MGT, while not zero, is a very small part of the overall chip cost. The area used for the MGTs is also small compared to everything else. You seem to be arguing that there are no market forces to force competitive pricing? Of course we will price the part to match market forces. Why not take advantage of all that superior engineering? Sounds like a bargain to me.