I need to recover data from a serial LVDS I/O stream running at over300 MHz. A reference 26 MHz clock is provided by the data source. So that clock needs to be bumped up to the data rate. The fast data is NOT phase aligned with the reference (or derived) clock. There is a 16-bit sync pattern at the start of every 'frame' of data. There is guarenteed to be at least one bit of '0' before the sync pattern starts
- between frames or from reset. It starts with a '1'. So a zero to one tansition will start the sync pattern if the 'logic' is 'searching' for the sync.
I have implemented some hardware that will work by using 4 phases of the fast clock. And I basically built a serial-to-parallel logic block that takes the data and deserializes it. The sync is searched for and detected. Once detected, the data is passed from the best phased clock domain. This all works fine and well at 100 MHz. I knew I would never get it up to the speed I need (Virtex4 LX25 -10) using the fabric. So I've looked in to using the SERDES IO technology. I've read the user guide and looked at some applications notes, but haven't found anything that really matches what I need. The logic that the app notes implement either rely on bit-syncronization techniques or a steady training pattern over a 'long' time. Those take too long to complete. I need to decide what phase of the clock to use (to ensure good data capture over a given frame) and pass that data on in less than the16-bit sync pattern. I know there are many possible solutions, but I was just posting this while I mess around with this problem. Anyone have any ideas?