Virtex 5 announced

ryanrs,

Yup. Now Peter and I are able to talk about Virtex 5.

Any questions?

65nm lives....both fabs!

Of course, it is early, but we are in ES sampling, and accepting folks for early adoption.

The release of the documention should be pretty good. I'd like to hear back on how good folks think it is.

Aust> Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be

>

I don't see any mention of a V5FX on your website. Can you tell us anything about the RocketIO on the Virtex5-FX yet?

Josh,

Always ask for what we didn't release? OK, that is fair. I wasn't very specific.

Details on FX in June.

For now, questions on LX.

Aust> >

I like the price of the eval boards!!

0.00 USD published price on Xilinx web!!

but well not available, guess the S3, S3E SAD STORY is repeating again or can we hope for better availability ??

hm the 0.00 USD price is eval without the Virtex-5 you have pictures of the boards, and still not available, what could be the reason for not selling eval boards that are made without the silicon?

must be some reason.

at least there is an v5 LX on the eval board picture :)

Antti

does LXT is include rocket IO?

ok, I am not fair - you specified LX not LXT

Antti

I am trying to be fair now, only asking LX questions :)

1) Xilinx website says to the general public that 'start designing' NOW to my understanding it means that software support is available NOW, or is there is any other way to see it?

2) the sysmonitor and ADC block that is present in V4 silicon but disabled by the design software, it is ripped out from V5 ?

hm, I am afraid all my others questions are related to FX so it would be fair to ask those. grrrr

Antti Lukats PS

ROTFL ROTFL ROTFL - this is was gooood laugh !!!! I had to re-register again to gain access to the support archive for the V5 user guide.

The download size was indicated as 9MB, made me interested what the heck is inside, NOW I know: the 9MB archive holds a single file, with famous name:

readme.txt

--------------- This is a placeholder file for the Virtex-5 SSO calculator. The calculator is due to be available with ISE8.2i software.

---------------

Hm at least it's now clear that V5 support must be included in ISE 8.2i and not 9.x ? Or will 8.2i only include that SSO Calculator?? But then what and when will actual V5 support be included in ISE/EDK?

Anayway it was good ROTFL ! ! ! The office is empty so I had no fear anyone calling the 911

Hi Austin,

This gives me the impression that V4-FX will be skipped - or at least customers will be pushed to V5-FX. This scares me quite a lot, actually.

OK, now some questions for the LX: How does the performance compares with V4-LX for simple things like Counter/Mux/Booth Multiplier.

Any trade-offs for the I/O? Full 3.3V tolerant/compatible? What's the core voltage?

That's it for now. I look forward to get hands on the (prelim.) datasheet.

Regards and thanks for you response,

Luc

Antti,

LXT is the LX with transceivers, yes.

We have not finished with the characterization of the transceivers.

Stay tuned for their announcement.

Aust> does LXT is include rocket IO?

Antti,

Software is available now.

It will be back, but not right away (in the software, it is definitely there in V5). Some things require a lot of characterization, and yield analysis, and we do not want to put customrs through what we did last time, for which we are very sorry, and promised not to do again.

We did get the sysmon working in V4, but too late to introduce it. It did allow us to debug the process of testing, yielding, etc. a complex analog block. What we learned was applied to V5.

Sorry. FX comes later. Transceivers come later, LXT. But the LXT will be here sooner than the FX or FXT parts.

The SSO calculator just missed by hours for this deadline. Try the link tomorrow. It was just one of those things where the key person who we needed to get us the numbers was out on vacation until last Monday, so we didn't have all the time we thought we had to get it ready.

Yes.

No, SSO will be there very shortly. ISE/EDK is another matter. I don't know the schedule on that. For Microblaze, that should be now (or very soon). For PPC, that waits for the FX.

Maybe someone who knows will email me.

Austin

scary eh?

the V5 performance data/comparison is given in currently available documentation, I just completed full fetch of the V5 docs and managed to get a quick peek.

core is 1.0 but thats no surprise. the 3.3V standards are all there of course

Antti

Antti schrieb:

You can either download a text editor from the Xilinx Website or select the "pencil and paper package" (5 weeks lead time) from the webshop to start your HDL capture now.

Kolja Sulimma

LOL LOL

I may borrow a paper and pencil Virtex5 HDL Design kit from my son I also (he had 4th birthday yesterday) I think - leadtime, hm when do I get home?.

jokes beside, he did like to play with the S3e sample pack (the dice game) too bad all my 3 sample pack PCBs are dead:( no wasnt faul play, they all died in my hands when inserting power plug (LTC power supply burned in).

Antti PS I hope there will be some tech news info also regarding V5, ok ok I can already say that

folks trash V4 and plans to use V4 if you can wait for V5.

similarly to S3e, V5 also has some nifty things added, small things that matter.

lb,

V4 FX is not skipped. It is most definitely being shipped right now. In fact the backlog was just cleared.

The basic fabric is a bit faster, but not a whole lot (perhaps only ~10%). The 6-LUT provides the most improvement by reducing the levels of logic. Anywhere from 58% speedup, with an average of 30% speedup over many hundreds of real customer designs from V4.

The carry logic is faster, and that is in the data sheet already.

1.0 Volt Vccint. 3.3V is the Vcco for the IO (or 2.5, or 1.8 or 1.5...).

Austin

Kolja,

Software is immediately available for the early access folks.

The general release of Virtex-5 LX (minus the LX330) will be in the initial release of 8.2i which is about a month away.

Aust> Antti schrieb:

Hi Austin,

I hope my smilies do get some others smile, well its a good day today (LOL + ROTFL) no I mean it, its good for change - really.

you are joking too :) please please can I email the ISE/EDK 9.1 to you?

FX vs FXT ?? in the website info roadmap there are

LX LXT SXT FXT

but no FX ?

can we hope FX earlier than FXT ? can we hope ethernet MAC earlier than _T parts?

or are those questions "FX only" ?

Antti

One last thought,

There are some that suspected we were close to an announcement, and decided to wind up the presses to spread forth much blather.

Too bad.

They are now left looking a bit foolish.

30% speedup today.

More density today.

Lower cost today.

Lower dynamic power, and equivalent static power, today.

Triple oxide (again) today. I don't think people really appreciate the triple oxide, and what it does for us: it allows us a third type of transistor which is optomized for stability (think about SEUs) for the config memory, and extremely low leakage, as well as for a optimized pass gates. This means we still have the lowest static leakage of anyone at both 90nm AND now at 65nm. Oh, there is NO 65nm FPGA, except ours.

The triple oxide process is something we pioneered with our fab partners. Read: both of them. Something that we can do, because our customers have chosen Xilinx, and made us large enough (read successful enough) to specify our own process to our fabrication partners! Think of that: what vendor has enough solid proven business to specify a process to more than one fab?

Imitation is the sincerest form of flattery, as STM now also has a triple oxide 90nm process. I am sure they will also offer it at 65nm, as they also realized how useful it was to their customers.

is a little late to the game. They are just now advertising 90nm triple oxide (by next calender quarter). Too bad. Too little, too late. That is not even 'fast follower'. That is a really late entrance onto the world stage by the leading player!

Now, for the second time, we have brought out this fantastic new technology, again on two fabs at once. No tricks, and no area hungry or goofy circuits for "maybe saving power." Just good old straight-forward simple engineering: use the right transistors for the right job. No risk to the customer, as the triple oxide technology worked great in V4, and is working great again in V5.

Austin

the basic LUT delay cant be much faster, it was pretty damn fast in V4 already ! however the 6 input LUT is not true 6 input LUT but two 5 input LUTs and a mux so if the mux delay is significant then 6 input function will we way slower than

5 input function, sure there is still performance gain over plain 4 LUT architecture.

Antti

Hi,

When can we expect Spartan 4? Six input LUTs seem to be a long over due change.

Dave

Antti,

Even my crystal ball is too foggy to see than far.

Aust> Hi Austin,