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maximum DDS clocking frequency on an Xilinx FPGA

Hello,

Does anyone know what is the maximum clocking frequency achievable on any Xilinx FPGA using the ISE's auto generated DDS core?

I need a cost effective way to test a high-speed DAC (>=500 MSPS) and need a digital pattern generator to drive my DAC input. So far the best solution I found is using an FPGA, but don't know how fast it can be.

The DDS needs to have performance better than 80dB SFDR, but doesn't need much frequency resolution (10 Hz is plenty). An pointers are welcome, thanks in advance.

Robin

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robin.tsang
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In Spartan-3 I am running a 32-bit DDS accumulator at 160 MHz. In Virtex-4 the "DSP Slice", which is a muliplier-accumulator with some extra hooks, runs guaranteed at 500 MHz, and involves zero external logic. If you want to go faster, you can use multiple accumulators and funnel them out through the parallel-to-serial converter that exists on every Virtex-4 output pin, and run 1 Gbps. If you want to go even faster, use the 3 Gbps multi-gigabit transceiver in Virtex-IIPro, or the up to 10 Gbps MGT in Virtex-IIProX.

You see, there are lots of options, all depending on the amount of mental effort you want to expend. But 10 Gbps is today's upper limit. Peter Alfke

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Peter Alfke

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