Hi there,
I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. I've already posted another question concerning a correct JTAG chain implementation a few days ago and gained pretty good response. But some problems remain... although on another topic:
I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed MGTs. The MGTs are located in two rows on each FPGA, each requiring their own MGT reference clock, i.e. four reference clock inputs have to be fed altogether plus at least one additional clock input for the core logic per FPGA. Because the FPGAs have to exchange data synchronously (via the standard GPIOs) I thought about using the same reference clocks for both FPGA and making them the same as the MGT reference. Unfortunately that leads to a clock signal that has to be distributed to at least 6 FPGA clock inputs.
I don't think that a regular low-jitter clock device (and it HAS to be low-jitter as for the reference for the MGTs) can drive 6 inputs over several centimeters. I already used the ICS843020 clock synthesizer in several other projects and wanted to use it again. Reason for the ICS is that it features a programmable output frequency in the range of 35 - 700 MHz. Problem is, the ICS843020 has only two outputs. The Epson EG2121CA device that is proposed in the Virtex-4 MGT user guide is not suitable because these devices are restricted to one fixed frequency.
Maybe a clock buffer or multi-output clock distribution device is the solution here, but I am afraid every additional device in the clock network would introduce additional jitter which is the most critical aspect in this application. Therefore I woul prefer a solution without those kind of devices... if possible.
Has anyone ever had a similar problem and knows about an adequate solution? Any help (if possible) is much appreciated. Thanks!
Regards Toni