I am a full professor in a US school and do research in the area of synthesis. I also teach logic design for Undergraduate students. I had a six month sabbatical recently in a design house and I used many FPGA cad tools. I would like to shed my experiences in this group.
I worked on 15 big designs, already coded, targeting both virtexII and StratixII. All the designs were in verilog and I used Xilinx XST and Altera QNS at the front end. I spent lot of time to see the quality of results from the synthesis tools. For 11 designs, QNS won both in area and final fmax. XST was not even comparable in the quality of results. QNS compiler seems to do very good job compared to XST. Also, QNS does very good job in removing redundant logic and registers. So in my experience, QNS is a much better logic synthesis tools compared to XST.
At the end of my sabbatical, I was able to use the latest (beta) synplify PRO. I did not have much time, but I did run these 15 designs targeting StartixII, as I was interested in comparing with the best known results. Synplify Pro did excellent job in implementing operators, and it found optimal five, six and seven inputs functions on the critical paths.
For my ten designs, Pro results were superior in terms of area and fmax compared to QNS. Synplify Pro has a very fast run time. For the remaining five designs, QNS seems to remove lot of redundant logic and registers, which pro did not remove. I did not have time to analyze these designs. QNS area was much smaller for these five designs.
I am back to my school and I use free XST and QNS tools. I am going to do more research using these tools. I would like to share my experience in this group. I am also interested in listening the quality of results from various tools.
Prof. John Smith email@example.com