Hello, everyone,
I am a new one. I am now doing a module design project. I follow the "modular design" chapter in "development System reference guide" of Xilinx. When I do the active module implementation phase, there are some error here.
--output pad net " a_out_OBUF"(a_out is the top-level outport and an output of module A either) has an illegal buffer.
--logical net " a_in_IBUF"(a_in is the top-level input and an input of module A either) has mutiple drivers. The possible drivers causing this are: pin O on block a_in_IBUF with type IBUF, pin PAD on block test_a/a_in_IBUF with type PAD.(test_a is the instance name of module A).
In this sample test, I just do 2 modules, and only a register in each module. in the top-level UCF file, I constrain the area of 2 modules and assign the top-level ports to IOBs.
So, how to resolve this problem.
Thank you.
regards. michel.