Has anyone had success interfacing Altera DPA with Xilinx ISERDES/OSERDES/IDELAY? Is 1 Gb/s/pin feasible for Virtex-5 and Stratix-II?
(did having both Altera and Xilinx on the same board cause some kind of exposion? :-)
I'm considering using a Virtex-5 LXT for its nice x8 PCI-E block in an otherwise mostly Altera design.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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