Virtual Pins in QuartusII


in one the last posts Christos recommended me to use Virtual Pins if I want the Fitter not to optimize registered unused signals away.

I have a module "sie.vhd" instantiated in my top level schematic design file "top_d.vhd".

The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. It is a registered signal which is not used at all.

(I use Altera QuartusII v 4.2).

In the Assignment Editor under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity "sie.vhd" with the filter "Register : pre-synthesis". Then I select ASSIGNMENT NAME=Virtual Pin, VALUE=On, ENABLED=Yes

After compilation I go into the NODE FINDER again to see if "Eop_not_recog" is still listed with the filter "Registers : post-fitting", but it is not. I conclude from this that the fitter optimized the node away although I defined the node as a Virtual pin.

Can someone explain to me what went wrong?

Thank you for your help.


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Somethin additional: Christos said: >One thing that might work is to drive them to outputs and then define >those >outputs as virtual pins with the assignment editor. >They will not be synthesised away.

In the QuartusII Help it is said: >This option should be specified only for I/O elements that become nodes >when imported to the top-level design.

So do I have to route the signal in the top level file to a FPGA pin and define it as VIRTUAL then or do I have to define the Port of the component "sie_rec.vhd" as virtual ?

It is not explained very clear.

Thank you.

Rgds André

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Hi Andre,

I think this thread should answer your question ...

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If you're trying to keep a wire/combinational logic, use the KEEP attribute. If you're trying to keep a register, use the Assignment Editor as described.


-- Pete

[ p s o m m e r f e l d (at) ]

Andr=E9s wrote:


design file

of the entity




virtual ?

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Define also in the top level the "Eop_not_recog" as a port. then use the assignment editor as you describe below but only this time for this port.



After compilation go to NODE FINDER and search for pins: all and you will find it.


I think you have found it and it is clear. The virtual pin can be only a pin, i.e. in, out or bidir and thus has to be routed up to the top level.

I hope it works for you. if not mail me directly ..

Christos dot Zamantzas at cern dot ch

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It's ok now, thank you Christos.


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Hi Andres,

To ensure an unnecessary register is not optimized away, use the "preserve" attribute. To do the same for a combinational node, use the "keep" attribute.

Virtual pins will also work, but as other posters have noted, they require that you connect the register to an I/O of your (sub) design. Virtual pins are really intended to support bottom-up design flows (create a module, compile in isolation, then bring module/placement/maybe routing) into the higher level design. So while they can be used to preserve registers, they're not as convenient as just using "preserve".

Here are some details from help on the altera website:

For details regarding the syntax for these attributes, refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.

The Keep Combinational Node attribute, keep or syn_keep, directs the compiler to keep a wire or net configuration intact during logic synthesis minimizations and netlist optimizations. When this attribute is applied, the Compiler will insert LCELL buffers in the design to maintain the node name. The option cannot preserve nodes that have no fan-out.

The Preserve Registers attribute, preserve or syn_preserve, directs the compiler not to m>> Hi,

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Vaughn Betz

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