Hello newsgroup people,
I am facing some problems when having the following pin declarations in my VHDL top level file.
(ispLEVER version 4.2) (device LFEC20E-5F672CES)
ATTRIBUTE PINL : STRING; ATTRIBUTE PINL OF Rst : SIGNAL IS "V25"; ATTRIBUTE PINL OF Clk_board : SIGNAL IS "V20"; ATTRIBUTE PINL OF Sdram_clk_out_p : SIGNAL IS "A15"; ATTRIBUTE PINL OF Sdram_clk_out_n : SIGNAL IS "B15"; ATTRIBUTE PINL OF Sdram_cke : SIGNAL IS "E17, B17"; ATTRIBUTE PINL OF Sdram_csn : SIGNAL IS "A24, A23"; ATTRIBUTE PINL OF Sdram_wen : SIGNAL IS "B22"; ATTRIBUTE PINL OF Sdram_casn : SIGNAL IS "A22"; ATTRIBUTE PINL OF Sdram_rasn : SIGNAL IS "A21"; ATTRIBUTE PINL OF Sdram_addr : SIGNAL IS "D19, A18, E20, E18, B18, F18, D18, F19, C18, G18, A19, G19, B19"; ATTRIBUTE PINL OF Sdram_ba : SIGNAL IS "B20, B21"; ATTRIBUTE PINL OF Sdram_dqm : SIGNAL IS "E16, F15"; ATTRIBUTE PINL OF Sdram_dqs : SIGNAL IS "A20, G15"; ATTRIBUTE PINL OF Sdram_dq : SIGNAL IS "C17, D17, C16, D16, F17, G17, F16, G16, C15, B16, C14, E14, D15, E15, F14, G14";
When compiling I get the following warning message: >Warning, attribute PINL given large bit vector width, potentially >unacceptable by place and route tools. Consider a string attribute >instead
Unfortunately I cannot find any answer in the HELP menu.
Has someone of you faced a similar problem ?
Thank you in advance.
Rgds