Quartus II: trace

Hello,

I'm a student and I am working on my Bachelor Lecture. Our tool is Quartus II, so I have a question. How can I trace a signal of a design, which doesn't "exist" after the Compilation (Post-Compilation)? Unfortunately I didn't find the answer neither on

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nor in altera documentations. I am very grateful, if somebody can help me. Thanks

Emrah

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emrah
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There may be a better way but I just made a "dummy" output port and assigned the signal in question to that dummy port. This was only for the simulation stage and I am aware that it could alter the routing for post-fit simulations. In my case, I was only using about 10% of the chip for that particular experiment so I wasn't very worried and so I did not make any comparisons of the fit/placement charts with and without my "dummy" output.

Rob Young

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Rob Young

Hi, I is there nobody who can tell me, how to trace a signal with Quartus II. I try it with the RTL-Viewer and with the Simulation-Waveform but it doesn't work!! I really need help from somebody who have expirience with Quartus II! I am nearly finished with my bachelor lecture... but I can't end it because my last job is to trace a input-signal in the Post-Compilation.

@Rob: Thanks, but my professor unfortunately don't want your method of resolution. :(

Thanks to all. Emrah

Reply to
emrah

Hi emrah,

If you are able to select the signal before compilation, either in the block diagram editor or in the node finder, you can tell Quartus to "Implement as output of Logic Cell" by using the Assignment Editor.

This will make sure that the signal is always present in the design (unless it's unnecessary and optimized away).

If you use VHDL or Verilog, look at the "keep" synthesis attribute, which does the same thing, but from your source code instead of from the Assignment Editor.

Good luck with these clues.

Best regards,

Ben

Reply to
Ben Twijnstra

Hi Ben, Thanks for your clues, but the signal I need is optimized away. Let me explain my problem in detail: We have a memory in our design and the inputs of this memory are optimized away. And my job is to get the exact delay of the memory!

Have you got another clue? Or idea?

Thanks Emrah

Reply to
emrah

What do you mean the inputs to the memory are optimized away? I don't know of any inputs to a memory that can be "optimized" away unless the memory is "optimized" away because the output is not driving anything.

The most common reason that a signal is not visible in simulation or net list is because the signal is between gates that are in the same LUT after synthesis. The inputs to a memory can not be combined into a LUT so that they no longer appear in your design. So they only way they can be removed is if the driver or receiver of the signal is no longer in the design. If you have an error in your design that results in a driver having no receiver or a receiver being driven by no driver, the tool will optimize that signal away. If this makes the part unusable, it will be removed as well. This can in turn create other signals that have no driver or receiver and they are removed as well... you get the idea. So you need to find the net that is connected to your RAM and find out if it really is connected or not.

You can find all the signals in your synthesized design by looking either at the equations or by bringing up one of the chip viewing tools. The one I use is the timing closure tool, since I am normally trying to improve timing. If you select any component and click the input net and/or output net buttons, it will show you the crow's path route. By viewing the equations window you can see the signal names on the component. If you want timing info, click on the icon for viewing timing info on the routes. This will not include the component delays, however. I normally use the timing analyzer for that.

If you want timing info, you can bring up the tool and select specific components. It can give you info on clock to clock, clock to output, input to clock or input to output. I'm not sure exactly what delays you want to find, but this tool should be able to give it to you. Once you have identified a path with your route of interest, you can list it with all the detail you need to examine any part of it.

--
Rick "rickman" Collins

rick.collins@XYarius.com
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rickman

Hi emrah,

Sounds like there's a problem in your code. If the inputs are optimized away, the RAM disappears as well, and so will its outputs go as well etc etc.

Any chance of you posting the code you're having trouble with? And, maybe, which version of the software you're using?

Best regards,

Ben

Reply to
Ben Twijnstra

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