Hi FPGA people,
I am using the VHDL module showed to synchronize my external asynchronous reset into my FPGA. When the external asynchronous reset gets inactive the flip flop chain makes sure that Reset_sync is deactivated synchronously.
The QuartusII (version 4.2) DESIGN ASSISTANT shows the following MEDIUM warning after synthesis:
External reset ARESET_N should be synchronized using two cascaded >registers
My question: Why should I synchronize the Areset_n to feed the Aset port of the flip flops ? If I did so there would arise the problem that the output of the flip flop chain (Reset_sync) would become uncertain when the PLL is not locked.
Should I let is that way or should I trust the recommendation of the DESIGN ASSISTANT tool ?
What is your opinion ?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY safe_reset IS PORT ( Clk : IN STD_LOGIC; Areset_n : IN STD_LOGIC; PLL_locked : IN STD_LOGIC; Reset_sync : OUT STD_LOGIC ); END safe_reset;
ARCHITECTURE rtl OF safe_reset IS
COMPONENT reset_flipflop PORT ( Clock : IN STD_LOGIC; Aset : IN STD_LOGIC; Data : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT;
SIGNAL l_q1 : STD_LOGIC; SIGNAL l_q2 : STD_LOGIC; SIGNAL l_q3 : STD_LOGIC; SIGNAL l_q4 : STD_LOGIC;
SIGNAL l_ena_shift : STD_LOGIC;
SIGNAL l_areset : STD_LOGIC;
BEGIN
Reset_sync l_ena_shift, Q => l_q1 ); i2 : reset_flipflop PORT MAP ( Clock => Clk, Aset => l_areset, Data => l_q1, Q => l_q2 ); i3 : reset_flipflop PORT MAP ( Clock => Clk, Aset => l_areset, Data => l_q2, Q => l_q3 ); i4 : reset_flipflop PORT MAP ( Clock => Clk, Aset => l_areset, Data => l_q3, Q => l_q4 );
END rtl;