Hi all,
The following VHDL code does not synthesize using XST 6.2.03:
----- start of fragment
-- The challenge is to define an entity that replicates
-- an input port (push button) to an output port (LED),
-- without declaring them in the entity's ports.
library ieee, unisim;
use ieee.std_logic_1164.all, unisim.vcomponents.all;
entity toplevel is -- wire input button to output LED -- without using a port declaration end entity toplevel;
architecture arch of toplevel is
signal BUTTON : std_logic; signal LED : std_logic; signal sig_led : std_logic; signal sig_button : std_logic;
attribute LOC : string;
attribute LOC of BUTTON : signal is "P22"; attribute LOC of LED : signal is "P20";
component OBUF is port (O: out std_ulogic; I: in std_ulogic); end component OBUF;
component IBUF is port (O: out std_ulogic; I: in std_ulogic); end component IBUF;
begin
button_buf : component IBUF port map(O => sig_button , I => BUTTON); led_buf : component OBUF port map(O => LED , I => not sig_led);
sig_led