I've included some code below that demonstrates the problem I am having. When I take the vhdl code shown, create a symbol file from it for Quartus II, then simulate it, there are glitches. q_out[7] changes 1 clock cycle too early, q_out[8] changes 2 clock cycles before q_out[7] q_out[9] changes 4 clock cycles before q_out[8] etc, etc
Please let me know if you can spot the problem.
-Phillip
------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all;
LIBRARY lpm; USE lpm.lpm_components.all;
ENTITY count_test IS PORT ( clock : in std_logic; updown : in std_logic; cnt_en : in std_logic; sclr : in std_logic; sset : in std_logic; q : out std_logic_vector(11 downto 0) ); END count_test;
ARCHITECTURE arch OF count_test IS SIGNAL q_out : std_logic_vector(11 downto 0); COMPONENT lpm_counter GENERIC ( lpm_width : POSITIVE; lpm_modulus : NATURAL := 0; lpm_direction : STRING := "UNUSED"; lpm_type : STRING := "LPM_COUNTER" ); PORT ( clock : IN STD_LOGIC ; updown : IN STD_LOGIC := '1'; cnt_en : IN STD_LOGIC := '1'; sset : IN STD_LOGIC := '0'; sclr : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); END COMPONENT; BEGIN q 12, lpm_type => "LPM_COUNTER", lpm_direction => "UNUSED" ) PORT MAP ( clock => clock, updown => updown, cnt_en => cnt_en, sclr => sclr, sset => sset, q => q_out ); END arch;