Hello: I'm newbie to Orcad 9.1 express, I'd like to synthesize a gal22v10 with a simple vhdl file just to test, I wrote the following file:
library ieee;
use ieee.std_logic_1164.all; use ieee.STD_LOGIC_UNSIGNED.all; use WORK.mylib1.all;
entity cmp_bdt is port( CLOCK : in std_logic; RESET : in std_logic; CK1 : out std_logic; CK2 : out std_logic; CK3 : out std_logic); end cmp_bdt;
architecture arch_behavioral of cmp_bdt is -- Component declarations -- Signal declarations signal cpt : std_logic_vector(2 downto 0); begin
GEN_CPT: process(CLOCK,RESET) begin if (CLOCK'event and CLOCK='1') then if (RESET='1') then CPT