Hi all,
Using Xilinx' XST, I want to add a VHDL "loc" constraint to a signal within a sub-component, without having to export the signal to the outside world via the entity's "port" declaration.
I tried the following:
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entity Blinky is port(CLK: in std_logic); end entity Blinky;
architecture arch of Blinky is signal LED: std_logic_vector(7 downto 0); attribute LOC: string; attribute LOC of LED: signal is "P11 P12 N12 P13 N14 L12 P14 K12"; process (CLK) is variable counter: std_logic_vector(23 downto 0); begin if rising_edge(CLK) then if counter = 0 then LED