I have a doubt.
when I create a signal like this:
signal abc std_logic_vector(3 downto 0);
after, when I write:
abc
VHDL Instantiation
Mar 04, 2005
5 Replies
"0000" until the end of the process "0001" thereafter assuming you are using a library that covers "+" for std_logic_vector. Run a simulation and see for yourself.
Consider using unsigned type and ieee.numeric_std for the "+" operation.
-- Mike Treseler
First, let me correct a small error. What you write would rather be with std_logic_vector(2 downto 0);
Then, the result is most certainly 001. Done it hundreds of time. Check it with a simulator.
yes, sorry for mistake... and if abc is std_logic_vector(0 to 2) ?
Same thing. 000 to 001.
Vectors always read left to right, without regard to the index limits or sequence.
-- Mike Treseler
And, at least in verilog, if you assign x[9:0] to y[0:9] they still go left to right. To reverse the bit order requires explicitly listing all the bits.
-- glen
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