SRL16E_1 primitive instantiation in VHDL

Eric,

Q1: I think you are missing the two lines below: Library UNISIM; use unisim.vcomponents.all;

Then, I don't think you need to declare the component.

Clean the project files and that should solve the error.

Q2:The timing report will tell you this. You can as well use the timing analyser.

Suggestion: You can use the primitive SRLC16E_1. it instantiate a SRL16 followed by a FF in the same CLB. Anyway, I think the tool is clever enough to place your FF in the same CLB

Hope this helps.

V> Hello,

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity srltest is port( clk : in std_logic; q : out std_logic ); end srltest;

architecture Behavioral of srltest is

-- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword

component SRL16 port ( Q : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CLK : in std_logic; D : in std_logic); end component;

-- Enter attributes here.

-- This is the data or pattern that gets circulated around. -- If the number of bits in the rotation cycle is less than 16, -- it will be the least significant bits (the rightmost bits) -- that get circulated. -- This example "0340" translates to binary 0000 0011 0100 0000 -- Only the 11 0100 0000 bits circulate in the 10 bit cycle below.

attribute init: string ; attribute init of SRL16_INSTANCE_NAME: label is "0340";

signal feedback : std_logic;

begin -- Component Instantiation for SRL16 is placed -- in architecture after the begin keyword.

-- SRL16 Circulating Bit Pattern Instantiation

-- The A inputs determine how many bits cycle around. -- The number of bits is one more than the A input. -- The maximum is 16 bits; the minimum is 1 bit. -- In this case shown below, there will be 10 bits.

SRL16_INSTANCE_NAME : SRL16 port map ( Q => feedback, A0 => '1', -- * 1 bit = 1 A1 => '0', -- * 2 bits = 0 A2 => '0', -- * 4 bits = 0 A3 => '1', -- * 8 bits = 8 so we get 1+0+0+8+1=10 bits CLK => clk, D => feedback );

-- generate an output pad

where is your library unisim statement?

Thanks for all the responses.

I was attempting to declare the component's interface myself, but I'm using the unisim declaration again now. I have now got an error at synthesis:

ERROR:Xst:764 - C:/code.vhd line 22: No default binding for component: . Generic is not on the entity. ERROR: XST failed

If I simply change SRL16E_1 to SRL16E the code passes through with no warnings or errors. Anyone know what is going on?

Eric.

library ieee; use ieee.std_logic_1164.all; library UNISIM; use UNISIM.VComponents.all;

entity ten_srl16s is port( Clock : in std_logic; CE : in std_logic; NewContent : in std_logic_vector (9 downto 0); Stimulus : in std_logic_vector(3 downto 0); Output : out std_logic_vector(9 downto 0) ); end ten_srl16s;

architecture structure of ten_srl16s is signal tempoutput : std_logic_vector(9 downto 0);

begin -- Instantiate the 10 srl16s instantiatesrl16s: for i in 0 to 9 generate cell : SRL16E_1 port map( Q=>tempoutput(i), A0=>stimulus(0), A1=>stimulus(1), A2=>stimulus(2), A3=>stimulus(3), CE=>CE, CLK=>Clock, D=>newcontent(i) ); end generate;

process(Clock) variable answer : std_logic_vector(9 downto 0); begin Output

The GENERATE will handle unrolling and labeling the elaborated processes based on the *single* label "instantiatesrl16s"

If the instances were outside of a generate, (they're not) then the designer would supply unique labels for each one, but cell_1: etc. not SRL16E_1:

The error occurs because SRL16E is in the library but SRL16E_1 is not.

-- Mike Treseler

But the SRL16E_1 component declaration follows directly after the SRL16E component declaration in unisim_VCOMP.vhd and they are both primitives.

The declarations are identical except for the difference in name. I can't understand why XST is happy with SRL16E in my most recently posted code but complains when I switch to SRL16E_1 by spitting out the above error message?

Eric.

Then you must have a mismatch between the component and the instance. Maybe SRL16E_1 requires an "INIT" generic while SRL16E does not.

-- Mike Treseler